1 //==- MachineScheduler.h - MachineInstr Scheduling Pass ----------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides a MachineSchedRegistry for registering alternative machine
11 // schedulers. A Target may provide an alternative scheduler implementation by
12 // implementing the following boilerplate:
14 // static ScheduleDAGInstrs *createCustomMachineSched(MachineSchedContext *C) {
15 // return new CustomMachineScheduler(C);
17 // static MachineSchedRegistry
18 // SchedCustomRegistry("custom", "Run my target's custom scheduler",
19 // createCustomMachineSched);
21 // Inside <Target>PassConfig:
22 // enablePass(&MachineSchedulerID);
23 // MachineSchedRegistry::setDefault(createCustomMachineSched);
25 //===----------------------------------------------------------------------===//
27 #ifndef LLVM_CODEGEN_MACHINESCHEDULER_H
28 #define LLVM_CODEGEN_MACHINESCHEDULER_H
30 #include "llvm/CodeGen/MachinePassRegistry.h"
31 #include "llvm/CodeGen/RegisterPressure.h"
32 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
36 extern cl::opt<bool> ForceTopDown;
37 extern cl::opt<bool> ForceBottomUp;
41 class MachineDominatorTree;
42 class MachineLoopInfo;
43 class RegisterClassInfo;
44 class ScheduleDAGInstrs;
47 /// MachineSchedContext provides enough context from the MachineScheduler pass
48 /// for the target to instantiate a scheduler.
49 struct MachineSchedContext {
51 const MachineLoopInfo *MLI;
52 const MachineDominatorTree *MDT;
53 const TargetPassConfig *PassConfig;
57 RegisterClassInfo *RegClassInfo;
59 MachineSchedContext();
60 virtual ~MachineSchedContext();
63 /// MachineSchedRegistry provides a selection of available machine instruction
65 class MachineSchedRegistry : public MachinePassRegistryNode {
67 typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineSchedContext *);
69 // RegisterPassParser requires a (misnamed) FunctionPassCtor type.
70 typedef ScheduleDAGCtor FunctionPassCtor;
72 static MachinePassRegistry Registry;
74 MachineSchedRegistry(const char *N, const char *D, ScheduleDAGCtor C)
75 : MachinePassRegistryNode(N, D, (MachinePassCtor)C) {
78 ~MachineSchedRegistry() { Registry.Remove(this); }
82 MachineSchedRegistry *getNext() const {
83 return (MachineSchedRegistry *)MachinePassRegistryNode::getNext();
85 static MachineSchedRegistry *getList() {
86 return (MachineSchedRegistry *)Registry.getList();
88 static ScheduleDAGCtor getDefault() {
89 return (ScheduleDAGCtor)Registry.getDefault();
91 static void setDefault(ScheduleDAGCtor C) {
92 Registry.setDefault((MachinePassCtor)C);
94 static void setDefault(StringRef Name) {
95 Registry.setDefault(Name);
97 static void setListener(MachinePassRegistryListener *L) {
98 Registry.setListener(L);
104 /// MachineSchedStrategy - Interface to the scheduling algorithm used by
106 class MachineSchedStrategy {
108 virtual ~MachineSchedStrategy() {}
110 /// Initialize the strategy after building the DAG for a new region.
111 virtual void initialize(ScheduleDAGMI *DAG) = 0;
113 /// Notify this strategy that all roots have been released (including those
114 /// that depend on EntrySU or ExitSU).
115 virtual void registerRoots() {}
117 /// Pick the next node to schedule, or return NULL. Set IsTopNode to true to
118 /// schedule the node at the top of the unscheduled region. Otherwise it will
119 /// be scheduled at the bottom.
120 virtual SUnit *pickNode(bool &IsTopNode) = 0;
122 /// \brief Scheduler callback to notify that a new subtree is scheduled.
123 virtual void scheduleTree(unsigned SubtreeID) {}
125 /// Notify MachineSchedStrategy that ScheduleDAGMI has scheduled an
126 /// instruction and updated scheduled/remaining flags in the DAG nodes.
127 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
129 /// When all predecessor dependencies have been resolved, free this node for
130 /// top-down scheduling.
131 virtual void releaseTopNode(SUnit *SU) = 0;
132 /// When all successor dependencies have been resolved, free this node for
133 /// bottom-up scheduling.
134 virtual void releaseBottomNode(SUnit *SU) = 0;
137 /// ReadyQueue encapsulates vector of "ready" SUnits with basic convenience
138 /// methods for pushing and removing nodes. ReadyQueue's are uniquely identified
139 /// by an ID. SUnit::NodeQueueId is a mask of the ReadyQueues the SUnit is in.
141 /// This is a convenience class that may be used by implementations of
142 /// MachineSchedStrategy.
146 std::vector<SUnit*> Queue;
149 ReadyQueue(unsigned id, const Twine &name): ID(id), Name(name.str()) {}
151 unsigned getID() const { return ID; }
153 StringRef getName() const { return Name; }
155 // SU is in this queue if it's NodeQueueID is a superset of this ID.
156 bool isInQueue(SUnit *SU) const { return (SU->NodeQueueId & ID); }
158 bool empty() const { return Queue.empty(); }
160 void clear() { Queue.clear(); }
162 unsigned size() const { return Queue.size(); }
164 typedef std::vector<SUnit*>::iterator iterator;
166 iterator begin() { return Queue.begin(); }
168 iterator end() { return Queue.end(); }
170 ArrayRef<SUnit*> elements() { return Queue; }
172 iterator find(SUnit *SU) {
173 return std::find(Queue.begin(), Queue.end(), SU);
176 void push(SUnit *SU) {
178 SU->NodeQueueId |= ID;
181 iterator remove(iterator I) {
182 (*I)->NodeQueueId &= ~ID;
184 unsigned idx = I - Queue.begin();
186 return Queue.begin() + idx;
189 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
194 /// Mutate the DAG as a postpass after normal DAG building.
195 class ScheduleDAGMutation {
197 virtual ~ScheduleDAGMutation() {}
199 virtual void apply(ScheduleDAGMI *DAG) = 0;
202 /// ScheduleDAGMI is an implementation of ScheduleDAGInstrs that schedules
203 /// machine instructions while updating LiveIntervals and tracking regpressure.
204 class ScheduleDAGMI : public ScheduleDAGInstrs {
207 RegisterClassInfo *RegClassInfo;
208 MachineSchedStrategy *SchedImpl;
210 /// Information about DAG subtrees. If DFSResult is NULL, then SchedulerTrees
212 SchedDFSResult *DFSResult;
213 BitVector ScheduledTrees;
215 /// Topo - A topological ordering for SUnits which permits fast IsReachable
216 /// and similar queries.
217 ScheduleDAGTopologicalSort Topo;
219 /// Ordered list of DAG postprocessing steps.
220 std::vector<ScheduleDAGMutation*> Mutations;
222 MachineBasicBlock::iterator LiveRegionEnd;
224 // Map each SU to its summary of pressure changes.
225 PressureDiffs SUPressureDiffs;
227 /// Register pressure in this region computed by initRegPressure.
228 IntervalPressure RegPressure;
229 RegPressureTracker RPTracker;
231 /// List of pressure sets that exceed the target's pressure limit before
232 /// scheduling, listed in increasing set ID order. Each pressure set is paired
233 /// with its max pressure in the currently scheduled regions.
234 std::vector<PressureChange> RegionCriticalPSets;
236 /// The top of the unscheduled zone.
237 MachineBasicBlock::iterator CurrentTop;
238 IntervalPressure TopPressure;
239 RegPressureTracker TopRPTracker;
241 /// The bottom of the unscheduled zone.
242 MachineBasicBlock::iterator CurrentBottom;
243 IntervalPressure BotPressure;
244 RegPressureTracker BotRPTracker;
246 /// Record the next node in a scheduled cluster.
247 const SUnit *NextClusterPred;
248 const SUnit *NextClusterSucc;
251 /// The number of instructions scheduled so far. Used to cut off the
252 /// scheduler at the point determined by misched-cutoff.
253 unsigned NumInstrsScheduled;
257 ScheduleDAGMI(MachineSchedContext *C, MachineSchedStrategy *S):
258 ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),
259 AA(C->AA), RegClassInfo(C->RegClassInfo), SchedImpl(S), DFSResult(0),
260 Topo(SUnits, &ExitSU), RPTracker(RegPressure), CurrentTop(),
261 TopRPTracker(TopPressure), CurrentBottom(), BotRPTracker(BotPressure),
262 NextClusterPred(NULL), NextClusterSucc(NULL) {
264 NumInstrsScheduled = 0;
268 virtual ~ScheduleDAGMI();
270 /// Add a postprocessing step to the DAG builder.
271 /// Mutations are applied in the order that they are added after normal DAG
272 /// building and before MachineSchedStrategy initialization.
274 /// ScheduleDAGMI takes ownership of the Mutation object.
275 void addMutation(ScheduleDAGMutation *Mutation) {
276 Mutations.push_back(Mutation);
279 /// \brief True if an edge can be added from PredSU to SuccSU without creating
281 bool canAddEdge(SUnit *SuccSU, SUnit *PredSU);
283 /// \brief Add a DAG edge to the given SU with the given predecessor
286 /// \returns true if the edge may be added without creating a cycle OR if an
287 /// equivalent edge already existed (false indicates failure).
288 bool addEdge(SUnit *SuccSU, const SDep &PredDep);
290 MachineBasicBlock::iterator top() const { return CurrentTop; }
291 MachineBasicBlock::iterator bottom() const { return CurrentBottom; }
293 /// Implement the ScheduleDAGInstrs interface for handling the next scheduling
294 /// region. This covers all instructions in a block, while schedule() may only
296 void enterRegion(MachineBasicBlock *bb,
297 MachineBasicBlock::iterator begin,
298 MachineBasicBlock::iterator end,
299 unsigned regioninstrs) LLVM_OVERRIDE;
301 /// Implement ScheduleDAGInstrs interface for scheduling a sequence of
302 /// reorderable instructions.
303 virtual void schedule();
305 /// Change the position of an instruction within the basic block and update
306 /// live ranges and region boundary iterators.
307 void moveInstruction(MachineInstr *MI, MachineBasicBlock::iterator InsertPos);
309 /// Get current register pressure for the top scheduled instructions.
310 const IntervalPressure &getTopPressure() const { return TopPressure; }
311 const RegPressureTracker &getTopRPTracker() const { return TopRPTracker; }
313 /// Get current register pressure for the bottom scheduled instructions.
314 const IntervalPressure &getBotPressure() const { return BotPressure; }
315 const RegPressureTracker &getBotRPTracker() const { return BotRPTracker; }
317 /// Get register pressure for the entire scheduling region before scheduling.
318 const IntervalPressure &getRegPressure() const { return RegPressure; }
320 const std::vector<PressureChange> &getRegionCriticalPSets() const {
321 return RegionCriticalPSets;
324 PressureDiff &getPressureDiff(const SUnit *SU) {
325 return SUPressureDiffs[SU->NodeNum];
328 const SUnit *getNextClusterPred() const { return NextClusterPred; }
330 const SUnit *getNextClusterSucc() const { return NextClusterSucc; }
332 /// Compute a DFSResult after DAG building is complete, and before any
333 /// queue comparisons.
334 void computeDFSResult();
336 /// Return a non-null DFS result if the scheduling strategy initialized it.
337 const SchedDFSResult *getDFSResult() const { return DFSResult; }
339 BitVector &getScheduledTrees() { return ScheduledTrees; }
341 /// Compute the cyclic critical path through the DAG.
342 unsigned computeCyclicCriticalPath();
344 void viewGraph(const Twine &Name, const Twine &Title) LLVM_OVERRIDE;
345 void viewGraph() LLVM_OVERRIDE;
348 // Top-Level entry points for the schedule() driver...
350 /// Call ScheduleDAGInstrs::buildSchedGraph with register pressure tracking
351 /// enabled. This sets up three trackers. RPTracker will cover the entire DAG
352 /// region, TopTracker and BottomTracker will be initialized to the top and
353 /// bottom of the DAG region without covereing any unscheduled instruction.
354 void buildDAGWithRegPressure();
356 /// Apply each ScheduleDAGMutation step in order. This allows different
357 /// instances of ScheduleDAGMI to perform custom DAG postprocessing.
358 void postprocessDAG();
360 /// Release ExitSU predecessors and setup scheduler queues.
361 void initQueues(ArrayRef<SUnit*> TopRoots, ArrayRef<SUnit*> BotRoots);
363 /// Move an instruction and update register pressure.
364 void scheduleMI(SUnit *SU, bool IsTopNode);
366 /// Update scheduler DAG and queues after scheduling an instruction.
367 void updateQueues(SUnit *SU, bool IsTopNode);
369 /// Reinsert debug_values recorded in ScheduleDAGInstrs::DbgValues.
370 void placeDebugValues();
372 /// \brief dump the scheduled Sequence.
373 void dumpSchedule() const;
377 void initRegPressure();
379 void updateScheduledPressure(const std::vector<unsigned> &NewMaxPressure);
381 bool checkSchedLimit();
383 void findRootsAndBiasEdges(SmallVectorImpl<SUnit*> &TopRoots,
384 SmallVectorImpl<SUnit*> &BotRoots);
386 void releaseSucc(SUnit *SU, SDep *SuccEdge);
387 void releaseSuccessors(SUnit *SU);
388 void releasePred(SUnit *SU, SDep *PredEdge);
389 void releasePredecessors(SUnit *SU);