1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code generation
11 // passes provided by the LLVM backend.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_PASSES_H
16 #define LLVM_CODEGEN_PASSES_H
18 #include "llvm/Pass.h"
19 #include "llvm/Target/TargetMachine.h"
25 class MachineFunctionPass;
27 class PassManagerBase;
29 class TargetRegisterClass;
37 /// Target-Independent Code Generator Pass Configuration Options.
39 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
40 /// to the internals of other CodeGen passes.
41 class TargetPassConfig : public ImmutablePass {
43 /// Pseudo Pass IDs. These are defined within TargetPassConfig because they
44 /// are unregistered pass IDs. They are only useful for use with
45 /// TargetPassConfig APIs to identify multiple occurrences of the same pass.
48 /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early
49 /// during codegen, on SSA form.
50 static char EarlyTailDuplicateID;
52 /// PostRAMachineLICM - A clone of the LICM pass that runs during late machine
53 /// optimization after regalloc.
54 static char PostRAMachineLICMID;
58 AnalysisID StartAfter;
65 PassConfigImpl *Impl; // Internal data structures
66 bool Initialized; // Flagged after all passes are configured.
68 // Target Pass Options
69 // Targets provide a default setting, user flags override.
73 /// Default setting for -enable-tail-merge on this target.
77 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
81 virtual ~TargetPassConfig();
85 /// Get the right type of TargetMachine for this target.
86 template<typename TMC> TMC &getTM() const {
87 return *static_cast<TMC*>(TM);
90 const TargetLowering *getTargetLowering() const {
91 return TM->getTargetLowering();
95 void setInitialized() { Initialized = true; }
97 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
99 /// setStartStopPasses - Set the StartAfter and StopAfter passes to allow
100 /// running only a portion of the normal code-gen pass sequence. If the
101 /// Start pass ID is zero, then compilation will begin at the normal point;
102 /// otherwise, clear the Started flag to indicate that passes should not be
103 /// added until the starting pass is seen. If the Stop pass ID is zero,
104 /// then compilation will continue to the end.
105 void setStartStopPasses(AnalysisID Start, AnalysisID Stop) {
108 Started = (StartAfter == 0);
111 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
113 bool getEnableTailMerge() const { return EnableTailMerge; }
114 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
116 /// Allow the target to override a specific pass without overriding the pass
117 /// pipeline. When passes are added to the standard pipeline at the
118 /// point where StandardID is expected, add TargetID in its place.
119 void substitutePass(AnalysisID StandardID, AnalysisID TargetID);
121 /// Insert InsertedPassID pass after TargetPassID pass.
122 void insertPass(AnalysisID TargetPassID, AnalysisID InsertedPassID);
124 /// Allow the target to enable a specific standard pass by default.
125 void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
127 /// Allow the target to disable a specific standard pass by default.
128 void disablePass(AnalysisID PassID) { substitutePass(PassID, 0); }
130 /// Return the pass substituted for StandardID by the target.
131 /// If no substitution exists, return StandardID.
132 AnalysisID getPassSubstitution(AnalysisID StandardID) const;
134 /// Return true if the optimized regalloc pipeline is enabled.
135 bool getOptimizeRegAlloc() const;
137 /// Add common target configurable passes that perform LLVM IR to IR
138 /// transforms following machine independent optimization.
139 virtual void addIRPasses();
141 /// Add passes to lower exception handling for the code generator.
142 void addPassesToHandleExceptions();
144 /// Add common passes that perform LLVM IR to IR transforms in preparation for
145 /// instruction selection.
146 virtual void addISelPrepare();
148 /// addInstSelector - This method should install an instruction selector pass,
149 /// which converts from LLVM code to machine instructions.
150 virtual bool addInstSelector() {
154 /// Add the complete, standard set of LLVM CodeGen passes.
155 /// Fully developed targets will not generally override this.
156 virtual void addMachinePasses();
159 // Helper to verify the analysis is really immutable.
160 void setOpt(bool &Opt, bool Val);
162 /// Methods with trivial inline returns are convenient points in the common
163 /// codegen pass pipeline where targets may insert passes. Methods with
164 /// out-of-line standard implementations are major CodeGen stages called by
165 /// addMachinePasses. Some targets may override major stages when inserting
166 /// passes is insufficient, but maintaining overriden stages is more work.
169 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
170 /// passes (which are run just before instruction selector).
171 virtual bool addPreISel() {
175 /// addMachineSSAOptimization - Add standard passes that optimize machine
176 /// instructions in SSA form.
177 virtual void addMachineSSAOptimization();
179 /// addPreRegAlloc - This method may be implemented by targets that want to
180 /// run passes immediately before register allocation. This should return
181 /// true if -print-machineinstrs should print after these passes.
182 virtual bool addPreRegAlloc() {
186 /// createTargetRegisterAllocator - Create the register allocator pass for
187 /// this target at the current optimization level.
188 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
190 /// addFastRegAlloc - Add the minimum set of target-independent passes that
191 /// are required for fast register allocation.
192 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
194 /// addOptimizedRegAlloc - Add passes related to register allocation.
195 /// LLVMTargetMachine provides standard regalloc passes for most targets.
196 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
198 /// addPreRewrite - Add passes to the optimized register allocation pipeline
199 /// after register allocation is complete, but before virtual registers are
200 /// rewritten to physical registers.
202 /// These passes must preserve VirtRegMap and LiveIntervals, and when running
203 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
204 /// When these passes run, VirtRegMap contains legal physreg assignments for
205 /// all virtual registers.
206 virtual bool addPreRewrite() {
210 /// addFinalizeRegAlloc - This method may be implemented by targets that want
211 /// to run passes within the regalloc pipeline, immediately after the register
212 /// allocation pass itself. These passes run as soon as virtual regisiters
213 /// have been rewritten to physical registers but before and other postRA
214 /// optimization happens. Targets that have marked instructions for bundling
215 /// must have finalized those bundles by the time these passes have run,
216 /// because subsequent passes are not guaranteed to be bundle-aware.
217 virtual bool addFinalizeRegAlloc() {
221 /// addPostRegAlloc - This method may be implemented by targets that want to
222 /// run passes after register allocation pass pipeline but before
223 /// prolog-epilog insertion. This should return true if -print-machineinstrs
224 /// should print after these passes.
225 virtual bool addPostRegAlloc() {
229 /// Add passes that optimize machine instructions after register allocation.
230 virtual void addMachineLateOptimization();
232 /// addPreSched2 - This method may be implemented by targets that want to
233 /// run passes after prolog-epilog insertion and before the second instruction
234 /// scheduling pass. This should return true if -print-machineinstrs should
235 /// print after these passes.
236 virtual bool addPreSched2() {
240 /// Add standard basic block placement passes.
241 virtual void addBlockPlacement();
243 /// addPreEmitPass - This pass may be implemented by targets that want to run
244 /// passes immediately before machine code is emitted. This should return
245 /// true if -print-machineinstrs should print out the code after the passes.
246 virtual bool addPreEmitPass() {
250 /// Utilities for targets to add passes to the pass manager.
253 /// Add a CodeGen pass at this point in the pipeline after checking overrides.
254 /// Return the pass that was added, or zero if no pass was added.
255 AnalysisID addPass(AnalysisID PassID);
257 /// Add a pass to the PassManager if that pass is supposed to be run, as
258 /// determined by the StartAfter and StopAfter options.
259 void addPass(Pass *P);
261 /// addMachinePasses helper to create the target-selected or overriden
263 FunctionPass *createRegAllocPass(bool Optimized);
265 /// printAndVerify - Add a pass to dump then verify the machine function, if
266 /// those steps are enabled.
268 void printAndVerify(const char *Banner);
272 /// List of target independent CodeGen pass IDs.
274 /// createUnreachableBlockEliminationPass - The LLVM code generator does not
275 /// work well with unreachable basic blocks (what live ranges make sense for a
276 /// block that cannot be reached?). As such, a code generator should either
277 /// not instruction select unreachable blocks, or run this pass as its
278 /// last LLVM modifying pass to clean up blocks that are not reachable from
280 FunctionPass *createUnreachableBlockEliminationPass();
282 /// MachineFunctionPrinter pass - This pass prints out the machine function to
283 /// the given stream as a debugging tool.
284 MachineFunctionPass *
285 createMachineFunctionPrinterPass(raw_ostream &OS,
286 const std::string &Banner ="");
288 /// MachineLoopInfo - This pass is a loop analysis pass.
289 extern char &MachineLoopInfoID;
291 /// MachineLoopRanges - This pass is an on-demand loop coverage analysis.
292 extern char &MachineLoopRangesID;
294 /// MachineDominators - This pass is a machine dominators analysis pass.
295 extern char &MachineDominatorsID;
297 /// EdgeBundles analysis - Bundle machine CFG edges.
298 extern char &EdgeBundlesID;
300 /// LiveVariables pass - This pass computes the set of blocks in which each
301 /// variable is life and sets machine operand kill flags.
302 extern char &LiveVariablesID;
304 /// PHIElimination - This pass eliminates machine instruction PHI nodes
305 /// by inserting copy instructions. This destroys SSA information, but is the
306 /// desired input for some register allocators. This pass is "required" by
307 /// these register allocator like this: AU.addRequiredID(PHIEliminationID);
308 extern char &PHIEliminationID;
310 /// StrongPHIElimination - This pass eliminates machine instruction PHI
311 /// nodes by inserting copy instructions. This destroys SSA information, but
312 /// is the desired input for some register allocators. This pass is
313 /// "required" by these register allocator like this:
314 /// AU.addRequiredID(PHIEliminationID);
315 /// This pass is still in development
316 extern char &StrongPHIEliminationID;
318 /// LiveIntervals - This analysis keeps track of the live ranges of virtual
319 /// and physical registers.
320 extern char &LiveIntervalsID;
322 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
323 extern char &LiveStacksID;
325 /// TwoAddressInstruction - This pass reduces two-address instructions to
326 /// use two operands. This destroys SSA information but it is desired by
327 /// register allocators.
328 extern char &TwoAddressInstructionPassID;
330 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
331 extern char &ProcessImplicitDefsID;
333 /// RegisterCoalescer - This pass merges live ranges to eliminate copies.
334 extern char &RegisterCoalescerID;
336 /// MachineScheduler - This pass schedules machine instructions.
337 extern char &MachineSchedulerID;
339 /// SpillPlacement analysis. Suggest optimal placement of spill code between
341 extern char &SpillPlacementID;
343 /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as
344 /// assigned in VirtRegMap.
345 extern char &VirtRegRewriterID;
347 /// UnreachableMachineBlockElimination - This pass removes unreachable
348 /// machine basic blocks.
349 extern char &UnreachableMachineBlockElimID;
351 /// DeadMachineInstructionElim - This pass removes dead machine instructions.
352 extern char &DeadMachineInstructionElimID;
354 /// FastRegisterAllocation Pass - This pass register allocates as fast as
355 /// possible. It is best suited for debug code where live ranges are short.
357 FunctionPass *createFastRegisterAllocator();
359 /// BasicRegisterAllocation Pass - This pass implements a degenerate global
360 /// register allocator using the basic regalloc framework.
362 FunctionPass *createBasicRegisterAllocator();
364 /// Greedy register allocation pass - This pass implements a global register
365 /// allocator for optimized builds.
367 FunctionPass *createGreedyRegisterAllocator();
369 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
370 /// Quadratic Prograaming (PBQP) based register allocator.
372 FunctionPass *createDefaultPBQPRegisterAllocator();
374 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
375 /// and eliminates abstract frame references.
376 extern char &PrologEpilogCodeInserterID;
378 /// ExpandPostRAPseudos - This pass expands pseudo instructions after
379 /// register allocation.
380 extern char &ExpandPostRAPseudosID;
382 /// createPostRAScheduler - This pass performs post register allocation
384 extern char &PostRASchedulerID;
386 /// BranchFolding - This pass performs machine code CFG based
387 /// optimizations to delete branches to branches, eliminate branches to
388 /// successor blocks (creating fall throughs), and eliminating branches over
390 extern char &BranchFolderPassID;
392 /// MachineFunctionPrinterPass - This pass prints out MachineInstr's.
393 extern char &MachineFunctionPrinterPassID;
395 /// TailDuplicate - Duplicate blocks with unconditional branches
396 /// into tails of their predecessors.
397 extern char &TailDuplicateID;
399 /// MachineTraceMetrics - This pass computes critical path and CPU resource
400 /// usage in an ensemble of traces.
401 extern char &MachineTraceMetricsID;
403 /// EarlyIfConverter - This pass performs if-conversion on SSA form by
404 /// inserting cmov instructions.
405 extern char &EarlyIfConverterID;
407 /// IfConverter - This pass performs machine code if conversion.
408 extern char &IfConverterID;
410 /// MachineBlockPlacement - This pass places basic blocks based on branch
412 extern char &MachineBlockPlacementID;
414 /// MachineBlockPlacementStats - This pass collects statistics about the
415 /// basic block placement using branch probabilities and block frequency
417 extern char &MachineBlockPlacementStatsID;
419 /// Code Placement - This pass optimize code placement and aligns loop
420 /// headers to target specific alignment boundary.
421 extern char &CodePlacementOptID;
423 /// GCLowering Pass - Performs target-independent LLVM IR transformations for
424 /// highly portable strategies.
426 FunctionPass *createGCLoweringPass();
428 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points
429 /// in machine code. Must be added very late during code generation, just
430 /// prior to output, and importantly after all CFG transformations (such as
432 extern char &GCMachineCodeAnalysisID;
434 /// Deleter Pass - Releases GC metadata.
436 FunctionPass *createGCInfoDeleter();
438 /// Creates a pass to print GC metadata.
440 FunctionPass *createGCInfoPrinter(raw_ostream &OS);
442 /// MachineCSE - This pass performs global CSE on machine instructions.
443 extern char &MachineCSEID;
445 /// MachineLICM - This pass performs LICM on machine instructions.
446 extern char &MachineLICMID;
448 /// MachineSinking - This pass performs sinking on machine instructions.
449 extern char &MachineSinkingID;
451 /// MachineCopyPropagation - This pass performs copy propagation on
452 /// machine instructions.
453 extern char &MachineCopyPropagationID;
455 /// PeepholeOptimizer - This pass performs peephole optimizations -
456 /// like extension and comparison eliminations.
457 extern char &PeepholeOptimizerID;
459 /// OptimizePHIs - This pass optimizes machine instruction PHIs
460 /// to take advantage of opportunities created during DAG legalization.
461 extern char &OptimizePHIsID;
463 /// StackSlotColoring - This pass performs stack slot coloring.
464 extern char &StackSlotColoringID;
466 /// createStackProtectorPass - This pass adds stack protectors to functions.
468 FunctionPass *createStackProtectorPass(const TargetLowering *tli);
470 /// createMachineVerifierPass - This pass verifies cenerated machine code
471 /// instructions for correctness.
473 FunctionPass *createMachineVerifierPass(const char *Banner = 0);
475 /// createDwarfEHPass - This pass mulches exception handling code into a form
476 /// adapted to code generation. Required if using dwarf exception handling.
477 FunctionPass *createDwarfEHPass(const TargetMachine *tm);
479 /// createSjLjEHPreparePass - This pass adapts exception handling code to use
480 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
482 FunctionPass *createSjLjEHPreparePass(const TargetLowering *tli);
484 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack
485 /// slots relative to one another and allocates base registers to access them
486 /// when it is estimated by the target to be out of range of normal frame
487 /// pointer or stack pointer index addressing.
488 extern char &LocalStackSlotAllocationID;
490 /// ExpandISelPseudos - This pass expands pseudo-instructions.
491 extern char &ExpandISelPseudosID;
493 /// createExecutionDependencyFixPass - This pass fixes execution time
494 /// problems with dependent instructions, such as switching execution
495 /// domains to match.
497 /// The pass will examine instructions using and defining registers in RC.
499 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
501 /// UnpackMachineBundles - This pass unpack machine instruction bundles.
502 extern char &UnpackMachineBundlesID;
504 /// FinalizeMachineBundles - This pass finalize machine instruction
505 /// bundles (created earlier, e.g. during pre-RA scheduling).
506 extern char &FinalizeMachineBundlesID;
508 } // End llvm namespace