1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code generation
11 // passes provided by the LLVM backend.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_PASSES_H
16 #define LLVM_CODEGEN_PASSES_H
18 #include "llvm/Pass.h"
19 #include "llvm/Target/TargetMachine.h"
25 class MachineFunctionPass;
28 class ScheduleDAGInstrs;
30 class TargetLoweringBase;
31 class TargetRegisterClass;
33 struct MachineSchedContext;
35 // The old pass manager infrastructure is hidden in a legacy namespace now.
37 class PassManagerBase;
39 using legacy::PassManagerBase;
41 /// Discriminated union of Pass ID types.
43 /// The PassConfig API prefers dealing with IDs because they are safer and more
44 /// efficient. IDs decouple configuration from instantiation. This way, when a
45 /// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to
46 /// refer to a Pass pointer after adding it to a pass manager, which deletes
47 /// redundant pass instances.
49 /// However, it is convient to directly instantiate target passes with
50 /// non-default ctors. These often don't have a registered PassInfo. Rather than
51 /// force all target passes to implement the pass registry boilerplate, allow
52 /// the PassConfig API to handle either type.
54 /// AnalysisID is sadly char*, so PointerIntPair won't work.
55 class IdentifyingPassPtr {
62 IdentifyingPassPtr() : P(nullptr), IsInstance(false) {}
63 IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr), IsInstance(false) {}
64 IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {}
66 bool isValid() const { return P; }
67 bool isInstance() const { return IsInstance; }
69 AnalysisID getID() const {
70 assert(!IsInstance && "Not a Pass ID");
73 Pass *getInstance() const {
74 assert(IsInstance && "Not a Pass Instance");
79 template <> struct isPodLike<IdentifyingPassPtr> {
80 static const bool value = true;
83 /// Target-Independent Code Generator Pass Configuration Options.
85 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
86 /// to the internals of other CodeGen passes.
87 class TargetPassConfig : public ImmutablePass {
89 /// Pseudo Pass IDs. These are defined within TargetPassConfig because they
90 /// are unregistered pass IDs. They are only useful for use with
91 /// TargetPassConfig APIs to identify multiple occurrences of the same pass.
94 /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early
95 /// during codegen, on SSA form.
96 static char EarlyTailDuplicateID;
98 /// PostRAMachineLICM - A clone of the LICM pass that runs during late machine
99 /// optimization after regalloc.
100 static char PostRAMachineLICMID;
104 AnalysisID StartBefore, StartAfter;
105 AnalysisID StopAfter;
108 bool AddingMachinePasses;
112 PassConfigImpl *Impl; // Internal data structures
113 bool Initialized; // Flagged after all passes are configured.
115 // Target Pass Options
116 // Targets provide a default setting, user flags override.
120 /// Default setting for -enable-tail-merge on this target.
121 bool EnableTailMerge;
124 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
125 // Dummy constructor.
128 ~TargetPassConfig() override;
132 /// Get the right type of TargetMachine for this target.
133 template<typename TMC> TMC &getTM() const {
134 return *static_cast<TMC*>(TM);
138 void setInitialized() { Initialized = true; }
140 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
142 /// Set the StartAfter, StartBefore and StopAfter passes to allow running only
143 /// a portion of the normal code-gen pass sequence.
145 /// If the StartAfter and StartBefore pass ID is zero, then compilation will
146 /// begin at the normal point; otherwise, clear the Started flag to indicate
147 /// that passes should not be added until the starting pass is seen. If the
148 /// Stop pass ID is zero, then compilation will continue to the end.
150 /// This function expects that at least one of the StartAfter or the
151 /// StartBefore pass IDs is null.
152 void setStartStopPasses(AnalysisID StartBefore, AnalysisID StartAfter,
153 AnalysisID StopAfter) {
155 assert(!StartBefore && "Start after and start before passes are given");
156 this->StartBefore = StartBefore;
157 this->StartAfter = StartAfter;
158 this->StopAfter = StopAfter;
159 Started = (StartAfter == nullptr) && (StartBefore == nullptr);
162 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
164 bool getEnableTailMerge() const { return EnableTailMerge; }
165 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
167 /// Allow the target to override a specific pass without overriding the pass
168 /// pipeline. When passes are added to the standard pipeline at the
169 /// point where StandardID is expected, add TargetID in its place.
170 void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID);
172 /// Insert InsertedPassID pass after TargetPassID pass.
173 void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID);
175 /// Allow the target to enable a specific standard pass by default.
176 void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
178 /// Allow the target to disable a specific standard pass by default.
179 void disablePass(AnalysisID PassID) {
180 substitutePass(PassID, IdentifyingPassPtr());
183 /// Return the pass substituted for StandardID by the target.
184 /// If no substitution exists, return StandardID.
185 IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const;
187 /// Return true if the optimized regalloc pipeline is enabled.
188 bool getOptimizeRegAlloc() const;
190 /// Return true if shrink wrapping is enabled.
191 bool getEnableShrinkWrap() const;
193 /// Return true if the default global register allocator is in use and
194 /// has not be overriden on the command line with '-regalloc=...'
195 bool usingDefaultRegAlloc() const;
197 /// Add common target configurable passes that perform LLVM IR to IR
198 /// transforms following machine independent optimization.
199 virtual void addIRPasses();
201 /// Add passes to lower exception handling for the code generator.
202 void addPassesToHandleExceptions();
204 /// Add pass to prepare the LLVM IR for code generation. This should be done
205 /// before exception handling preparation passes.
206 virtual void addCodeGenPrepare();
208 /// Add common passes that perform LLVM IR to IR transforms in preparation for
209 /// instruction selection.
210 virtual void addISelPrepare();
212 /// addInstSelector - This method should install an instruction selector pass,
213 /// which converts from LLVM code to machine instructions.
214 virtual bool addInstSelector() {
218 /// Add the complete, standard set of LLVM CodeGen passes.
219 /// Fully developed targets will not generally override this.
220 virtual void addMachinePasses();
222 /// Create an instance of ScheduleDAGInstrs to be run within the standard
223 /// MachineScheduler pass for this function and target at the current
224 /// optimization level.
226 /// This can also be used to plug a new MachineSchedStrategy into an instance
227 /// of the standard ScheduleDAGMI:
228 /// return new ScheduleDAGMI(C, make_unique<MyStrategy>(C), /* IsPostRA= */false)
230 /// Return NULL to select the default (generic) machine scheduler.
231 virtual ScheduleDAGInstrs *
232 createMachineScheduler(MachineSchedContext *C) const {
236 /// Similar to createMachineScheduler but used when postRA machine scheduling
238 virtual ScheduleDAGInstrs *
239 createPostMachineScheduler(MachineSchedContext *C) const {
244 // Helper to verify the analysis is really immutable.
245 void setOpt(bool &Opt, bool Val);
247 /// Methods with trivial inline returns are convenient points in the common
248 /// codegen pass pipeline where targets may insert passes. Methods with
249 /// out-of-line standard implementations are major CodeGen stages called by
250 /// addMachinePasses. Some targets may override major stages when inserting
251 /// passes is insufficient, but maintaining overriden stages is more work.
254 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
255 /// passes (which are run just before instruction selector).
256 virtual bool addPreISel() {
260 /// addMachineSSAOptimization - Add standard passes that optimize machine
261 /// instructions in SSA form.
262 virtual void addMachineSSAOptimization();
264 /// Add passes that optimize instruction level parallelism for out-of-order
265 /// targets. These passes are run while the machine code is still in SSA
266 /// form, so they can use MachineTraceMetrics to control their heuristics.
268 /// All passes added here should preserve the MachineDominatorTree,
269 /// MachineLoopInfo, and MachineTraceMetrics analyses.
270 virtual bool addILPOpts() {
274 /// This method may be implemented by targets that want to run passes
275 /// immediately before register allocation.
276 virtual void addPreRegAlloc() { }
278 /// createTargetRegisterAllocator - Create the register allocator pass for
279 /// this target at the current optimization level.
280 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
282 /// addFastRegAlloc - Add the minimum set of target-independent passes that
283 /// are required for fast register allocation.
284 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
286 /// addOptimizedRegAlloc - Add passes related to register allocation.
287 /// LLVMTargetMachine provides standard regalloc passes for most targets.
288 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
290 /// addPreRewrite - Add passes to the optimized register allocation pipeline
291 /// after register allocation is complete, but before virtual registers are
292 /// rewritten to physical registers.
294 /// These passes must preserve VirtRegMap and LiveIntervals, and when running
295 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
296 /// When these passes run, VirtRegMap contains legal physreg assignments for
297 /// all virtual registers.
298 virtual bool addPreRewrite() {
302 /// This method may be implemented by targets that want to run passes after
303 /// register allocation pass pipeline but before prolog-epilog insertion.
304 virtual void addPostRegAlloc() { }
306 /// Add passes that optimize machine instructions after register allocation.
307 virtual void addMachineLateOptimization();
309 /// This method may be implemented by targets that want to run passes after
310 /// prolog-epilog insertion and before the second instruction scheduling pass.
311 virtual void addPreSched2() { }
313 /// addGCPasses - Add late codegen passes that analyze code for garbage
314 /// collection. This should return true if GC info should be printed after
316 virtual bool addGCPasses();
318 /// Add standard basic block placement passes.
319 virtual void addBlockPlacement();
321 /// This pass may be implemented by targets that want to run passes
322 /// immediately before machine code is emitted.
323 virtual void addPreEmitPass() { }
325 /// Utilities for targets to add passes to the pass manager.
328 /// Add a CodeGen pass at this point in the pipeline after checking overrides.
329 /// Return the pass that was added, or zero if no pass was added.
330 /// @p printAfter if true and adding a machine function pass add an extra
331 /// machine printer pass afterwards
332 /// @p verifyAfter if true and adding a machine function pass add an extra
333 /// machine verification pass afterwards.
334 AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true,
335 bool printAfter = true);
337 /// Add a pass to the PassManager if that pass is supposed to be run, as
338 /// determined by the StartAfter and StopAfter options. Takes ownership of the
340 /// @p printAfter if true and adding a machine function pass add an extra
341 /// machine printer pass afterwards
342 /// @p verifyAfter if true and adding a machine function pass add an extra
343 /// machine verification pass afterwards.
344 void addPass(Pass *P, bool verifyAfter = true, bool printAfter = true);
346 /// addMachinePasses helper to create the target-selected or overriden
348 FunctionPass *createRegAllocPass(bool Optimized);
350 /// printAndVerify - Add a pass to dump then verify the machine function, if
351 /// those steps are enabled.
353 void printAndVerify(const std::string &Banner);
355 /// Add a pass to print the machine function if printing is enabled.
356 void addPrintPass(const std::string &Banner);
358 /// Add a pass to perform basic verification of the machine function if
359 /// verification is enabled.
360 void addVerifyPass(const std::string &Banner);
364 /// List of target independent CodeGen pass IDs.
366 FunctionPass *createAtomicExpandPass(const TargetMachine *TM);
368 /// createUnreachableBlockEliminationPass - The LLVM code generator does not
369 /// work well with unreachable basic blocks (what live ranges make sense for a
370 /// block that cannot be reached?). As such, a code generator should either
371 /// not instruction select unreachable blocks, or run this pass as its
372 /// last LLVM modifying pass to clean up blocks that are not reachable from
374 FunctionPass *createUnreachableBlockEliminationPass();
376 /// MachineFunctionPrinter pass - This pass prints out the machine function to
377 /// the given stream as a debugging tool.
378 MachineFunctionPass *
379 createMachineFunctionPrinterPass(raw_ostream &OS,
380 const std::string &Banner ="");
382 /// MIRPrinting pass - this pass prints out the LLVM IR into the given stream
383 /// using the MIR serialization format.
384 MachineFunctionPass *createPrintMIRPass(raw_ostream &OS);
386 /// createCodeGenPreparePass - Transform the code to expose more pattern
387 /// matching during instruction selection.
388 FunctionPass *createCodeGenPreparePass(const TargetMachine *TM = nullptr);
390 /// AtomicExpandID -- Lowers atomic operations in terms of either cmpxchg
391 /// load-linked/store-conditional loops.
392 extern char &AtomicExpandID;
394 /// MachineLoopInfo - This pass is a loop analysis pass.
395 extern char &MachineLoopInfoID;
397 /// MachineDominators - This pass is a machine dominators analysis pass.
398 extern char &MachineDominatorsID;
400 /// MachineDominanaceFrontier - This pass is a machine dominators analysis pass.
401 extern char &MachineDominanceFrontierID;
403 /// EdgeBundles analysis - Bundle machine CFG edges.
404 extern char &EdgeBundlesID;
406 /// LiveVariables pass - This pass computes the set of blocks in which each
407 /// variable is life and sets machine operand kill flags.
408 extern char &LiveVariablesID;
410 /// PHIElimination - This pass eliminates machine instruction PHI nodes
411 /// by inserting copy instructions. This destroys SSA information, but is the
412 /// desired input for some register allocators. This pass is "required" by
413 /// these register allocator like this: AU.addRequiredID(PHIEliminationID);
414 extern char &PHIEliminationID;
416 /// LiveIntervals - This analysis keeps track of the live ranges of virtual
417 /// and physical registers.
418 extern char &LiveIntervalsID;
420 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
421 extern char &LiveStacksID;
423 /// TwoAddressInstruction - This pass reduces two-address instructions to
424 /// use two operands. This destroys SSA information but it is desired by
425 /// register allocators.
426 extern char &TwoAddressInstructionPassID;
428 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
429 extern char &ProcessImplicitDefsID;
431 /// RegisterCoalescer - This pass merges live ranges to eliminate copies.
432 extern char &RegisterCoalescerID;
434 /// MachineScheduler - This pass schedules machine instructions.
435 extern char &MachineSchedulerID;
437 /// PostMachineScheduler - This pass schedules machine instructions postRA.
438 extern char &PostMachineSchedulerID;
440 /// SpillPlacement analysis. Suggest optimal placement of spill code between
442 extern char &SpillPlacementID;
444 /// ShrinkWrap pass. Look for the best place to insert save and restore
445 // instruction and update the MachineFunctionInfo with that information.
446 extern char &ShrinkWrapID;
448 /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as
449 /// assigned in VirtRegMap.
450 extern char &VirtRegRewriterID;
452 /// UnreachableMachineBlockElimination - This pass removes unreachable
453 /// machine basic blocks.
454 extern char &UnreachableMachineBlockElimID;
456 /// DeadMachineInstructionElim - This pass removes dead machine instructions.
457 extern char &DeadMachineInstructionElimID;
459 /// FastRegisterAllocation Pass - This pass register allocates as fast as
460 /// possible. It is best suited for debug code where live ranges are short.
462 FunctionPass *createFastRegisterAllocator();
464 /// BasicRegisterAllocation Pass - This pass implements a degenerate global
465 /// register allocator using the basic regalloc framework.
467 FunctionPass *createBasicRegisterAllocator();
469 /// Greedy register allocation pass - This pass implements a global register
470 /// allocator for optimized builds.
472 FunctionPass *createGreedyRegisterAllocator();
474 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
475 /// Quadratic Prograaming (PBQP) based register allocator.
477 FunctionPass *createDefaultPBQPRegisterAllocator();
479 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
480 /// and eliminates abstract frame references.
481 extern char &PrologEpilogCodeInserterID;
483 /// ExpandPostRAPseudos - This pass expands pseudo instructions after
484 /// register allocation.
485 extern char &ExpandPostRAPseudosID;
487 /// createPostRAScheduler - This pass performs post register allocation
489 extern char &PostRASchedulerID;
491 /// BranchFolding - This pass performs machine code CFG based
492 /// optimizations to delete branches to branches, eliminate branches to
493 /// successor blocks (creating fall throughs), and eliminating branches over
495 extern char &BranchFolderPassID;
497 /// MachineFunctionPrinterPass - This pass prints out MachineInstr's.
498 extern char &MachineFunctionPrinterPassID;
500 /// MIRPrintingPass - this pass prints out the LLVM IR using the MIR
501 /// serialization format.
502 extern char &MIRPrintingPassID;
504 /// TailDuplicate - Duplicate blocks with unconditional branches
505 /// into tails of their predecessors.
506 extern char &TailDuplicateID;
508 /// MachineTraceMetrics - This pass computes critical path and CPU resource
509 /// usage in an ensemble of traces.
510 extern char &MachineTraceMetricsID;
512 /// EarlyIfConverter - This pass performs if-conversion on SSA form by
513 /// inserting cmov instructions.
514 extern char &EarlyIfConverterID;
516 /// This pass performs instruction combining using trace metrics to estimate
517 /// critical-path and resource depth.
518 extern char &MachineCombinerID;
520 /// StackSlotColoring - This pass performs stack coloring and merging.
521 /// It merges disjoint allocas to reduce the stack size.
522 extern char &StackColoringID;
524 /// IfConverter - This pass performs machine code if conversion.
525 extern char &IfConverterID;
527 FunctionPass *createIfConverter(std::function<bool(const Function &)> Ftor);
529 /// MachineBlockPlacement - This pass places basic blocks based on branch
531 extern char &MachineBlockPlacementID;
533 /// MachineBlockPlacementStats - This pass collects statistics about the
534 /// basic block placement using branch probabilities and block frequency
536 extern char &MachineBlockPlacementStatsID;
538 /// GCLowering Pass - Used by gc.root to perform its default lowering
540 FunctionPass *createGCLoweringPass();
542 /// ShadowStackGCLowering - Implements the custom lowering mechanism
543 /// used by the shadow stack GC. Only runs on functions which opt in to
544 /// the shadow stack collector.
545 FunctionPass *createShadowStackGCLoweringPass();
547 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points
548 /// in machine code. Must be added very late during code generation, just
549 /// prior to output, and importantly after all CFG transformations (such as
551 extern char &GCMachineCodeAnalysisID;
553 /// Creates a pass to print GC metadata.
555 FunctionPass *createGCInfoPrinter(raw_ostream &OS);
557 /// MachineCSE - This pass performs global CSE on machine instructions.
558 extern char &MachineCSEID;
560 /// ImplicitNullChecks - This pass folds null pointer checks into nearby
561 /// memory operations.
562 extern char &ImplicitNullChecksID;
564 /// MachineLICM - This pass performs LICM on machine instructions.
565 extern char &MachineLICMID;
567 /// MachineSinking - This pass performs sinking on machine instructions.
568 extern char &MachineSinkingID;
570 /// MachineCopyPropagation - This pass performs copy propagation on
571 /// machine instructions.
572 extern char &MachineCopyPropagationID;
574 /// PeepholeOptimizer - This pass performs peephole optimizations -
575 /// like extension and comparison eliminations.
576 extern char &PeepholeOptimizerID;
578 /// OptimizePHIs - This pass optimizes machine instruction PHIs
579 /// to take advantage of opportunities created during DAG legalization.
580 extern char &OptimizePHIsID;
582 /// StackSlotColoring - This pass performs stack slot coloring.
583 extern char &StackSlotColoringID;
585 /// createStackProtectorPass - This pass adds stack protectors to functions.
587 FunctionPass *createStackProtectorPass(const TargetMachine *TM);
589 /// createMachineVerifierPass - This pass verifies cenerated machine code
590 /// instructions for correctness.
592 FunctionPass *createMachineVerifierPass(const std::string& Banner);
594 /// createDwarfEHPass - This pass mulches exception handling code into a form
595 /// adapted to code generation. Required if using dwarf exception handling.
596 FunctionPass *createDwarfEHPass(const TargetMachine *TM);
598 /// createWinEHPass - Prepares personality functions used by MSVC on Windows,
599 /// in addition to the Itanium LSDA based personalities.
600 FunctionPass *createWinEHPass(const TargetMachine *TM);
602 /// createSjLjEHPreparePass - This pass adapts exception handling code to use
603 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
605 FunctionPass *createSjLjEHPreparePass();
607 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack
608 /// slots relative to one another and allocates base registers to access them
609 /// when it is estimated by the target to be out of range of normal frame
610 /// pointer or stack pointer index addressing.
611 extern char &LocalStackSlotAllocationID;
613 /// ExpandISelPseudos - This pass expands pseudo-instructions.
614 extern char &ExpandISelPseudosID;
616 /// createExecutionDependencyFixPass - This pass fixes execution time
617 /// problems with dependent instructions, such as switching execution
618 /// domains to match.
620 /// The pass will examine instructions using and defining registers in RC.
622 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
624 /// UnpackMachineBundles - This pass unpack machine instruction bundles.
625 extern char &UnpackMachineBundlesID;
628 createUnpackMachineBundles(std::function<bool(const Function &)> Ftor);
630 /// FinalizeMachineBundles - This pass finalize machine instruction
631 /// bundles (created earlier, e.g. during pre-RA scheduling).
632 extern char &FinalizeMachineBundlesID;
634 /// StackMapLiveness - This pass analyses the register live-out set of
635 /// stackmap/patchpoint intrinsics and attaches the calculated information to
636 /// the intrinsic for later emission to the StackMap.
637 extern char &StackMapLivenessID;
639 /// createJumpInstrTables - This pass creates jump-instruction tables.
640 ModulePass *createJumpInstrTablesPass();
642 /// createForwardControlFlowIntegrityPass - This pass adds control-flow
644 ModulePass *createForwardControlFlowIntegrityPass();
646 /// InterleavedAccess Pass - This pass identifies and matches interleaved
647 /// memory accesses to target specific intrinsics.
649 FunctionPass *createInterleavedAccessPass(const TargetMachine *TM);
650 } // End llvm namespace
652 /// Target machine pass initializer for passes with dependencies. Use with
653 /// INITIALIZE_TM_PASS_END.
654 #define INITIALIZE_TM_PASS_BEGIN INITIALIZE_PASS_BEGIN
656 /// Target machine pass initializer for passes with dependencies. Use with
657 /// INITIALIZE_TM_PASS_BEGIN.
658 #define INITIALIZE_TM_PASS_END(passName, arg, name, cfg, analysis) \
659 PassInfo *PI = new PassInfo(name, arg, & passName ::ID, \
660 PassInfo::NormalCtor_t(callDefaultCtor< passName >), cfg, analysis, \
661 PassInfo::TargetMachineCtor_t(callTargetMachineCtor< passName >)); \
662 Registry.registerPass(*PI, true); \
665 void llvm::initialize##passName##Pass(PassRegistry &Registry) { \
666 CALL_ONCE_INITIALIZATION(initialize##passName##PassOnce) \
669 /// This initializer registers TargetMachine constructor, so the pass being
670 /// initialized can use target dependent interfaces. Please do not move this
671 /// macro to be together with INITIALIZE_PASS, which is a complete target
672 /// independent initializer, and we don't want to make libScalarOpts depend
674 #define INITIALIZE_TM_PASS(passName, arg, name, cfg, analysis) \
675 INITIALIZE_TM_PASS_BEGIN(passName, arg, name, cfg, analysis) \
676 INITIALIZE_TM_PASS_END(passName, arg, name, cfg, analysis)