1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code generation
11 // passes provided by the LLVM backend.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_PASSES_H
16 #define LLVM_CODEGEN_PASSES_H
18 #include "llvm/Pass.h"
19 #include "llvm/Target/TargetMachine.h"
25 class MachineFunctionPass;
28 class ScheduleDAGInstrs;
30 class TargetLoweringBase;
31 class TargetRegisterClass;
33 struct MachineSchedContext;
35 // The old pass manager infrastructure is hidden in a legacy namespace now.
37 class PassManagerBase;
39 using legacy::PassManagerBase;
41 /// Discriminated union of Pass ID types.
43 /// The PassConfig API prefers dealing with IDs because they are safer and more
44 /// efficient. IDs decouple configuration from instantiation. This way, when a
45 /// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to
46 /// refer to a Pass pointer after adding it to a pass manager, which deletes
47 /// redundant pass instances.
49 /// However, it is convient to directly instantiate target passes with
50 /// non-default ctors. These often don't have a registered PassInfo. Rather than
51 /// force all target passes to implement the pass registry boilerplate, allow
52 /// the PassConfig API to handle either type.
54 /// AnalysisID is sadly char*, so PointerIntPair won't work.
55 class IdentifyingPassPtr {
62 IdentifyingPassPtr() : P(0), IsInstance(false) {}
63 IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr), IsInstance(false) {}
64 IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {}
66 bool isValid() const { return P; }
67 bool isInstance() const { return IsInstance; }
69 AnalysisID getID() const {
70 assert(!IsInstance && "Not a Pass ID");
73 Pass *getInstance() const {
74 assert(IsInstance && "Not a Pass Instance");
79 template <> struct isPodLike<IdentifyingPassPtr> {
80 static const bool value = true;
83 /// Target-Independent Code Generator Pass Configuration Options.
85 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
86 /// to the internals of other CodeGen passes.
87 class TargetPassConfig : public ImmutablePass {
89 /// Pseudo Pass IDs. These are defined within TargetPassConfig because they
90 /// are unregistered pass IDs. They are only useful for use with
91 /// TargetPassConfig APIs to identify multiple occurrences of the same pass.
94 /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early
95 /// during codegen, on SSA form.
96 static char EarlyTailDuplicateID;
98 /// PostRAMachineLICM - A clone of the LICM pass that runs during late machine
99 /// optimization after regalloc.
100 static char PostRAMachineLICMID;
104 AnalysisID StartAfter;
105 AnalysisID StopAfter;
111 PassConfigImpl *Impl; // Internal data structures
112 bool Initialized; // Flagged after all passes are configured.
114 // Target Pass Options
115 // Targets provide a default setting, user flags override.
119 /// Default setting for -enable-tail-merge on this target.
120 bool EnableTailMerge;
123 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
124 // Dummy constructor.
127 virtual ~TargetPassConfig();
131 /// Get the right type of TargetMachine for this target.
132 template<typename TMC> TMC &getTM() const {
133 return *static_cast<TMC*>(TM);
136 const TargetLowering *getTargetLowering() const {
137 return TM->getTargetLowering();
141 void setInitialized() { Initialized = true; }
143 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
145 /// setStartStopPasses - Set the StartAfter and StopAfter passes to allow
146 /// running only a portion of the normal code-gen pass sequence. If the
147 /// Start pass ID is zero, then compilation will begin at the normal point;
148 /// otherwise, clear the Started flag to indicate that passes should not be
149 /// added until the starting pass is seen. If the Stop pass ID is zero,
150 /// then compilation will continue to the end.
151 void setStartStopPasses(AnalysisID Start, AnalysisID Stop) {
154 Started = (StartAfter == 0);
157 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
159 bool getEnableTailMerge() const { return EnableTailMerge; }
160 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
162 /// Allow the target to override a specific pass without overriding the pass
163 /// pipeline. When passes are added to the standard pipeline at the
164 /// point where StandardID is expected, add TargetID in its place.
165 void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID);
167 /// Insert InsertedPassID pass after TargetPassID pass.
168 void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID);
170 /// Allow the target to enable a specific standard pass by default.
171 void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
173 /// Allow the target to disable a specific standard pass by default.
174 void disablePass(AnalysisID PassID) {
175 substitutePass(PassID, IdentifyingPassPtr());
178 /// Return the pass substituted for StandardID by the target.
179 /// If no substitution exists, return StandardID.
180 IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const;
182 /// Return true if the optimized regalloc pipeline is enabled.
183 bool getOptimizeRegAlloc() const;
185 /// Add common target configurable passes that perform LLVM IR to IR
186 /// transforms following machine independent optimization.
187 virtual void addIRPasses();
189 /// Add passes to lower exception handling for the code generator.
190 void addPassesToHandleExceptions();
192 /// Add pass to prepare the LLVM IR for code generation. This should be done
193 /// before exception handling preparation passes.
194 virtual void addCodeGenPrepare();
196 /// Add common passes that perform LLVM IR to IR transforms in preparation for
197 /// instruction selection.
198 virtual void addISelPrepare();
200 /// addInstSelector - This method should install an instruction selector pass,
201 /// which converts from LLVM code to machine instructions.
202 virtual bool addInstSelector() {
206 /// Add the complete, standard set of LLVM CodeGen passes.
207 /// Fully developed targets will not generally override this.
208 virtual void addMachinePasses();
210 /// Create an instance of ScheduleDAGInstrs to be run within the standard
211 /// MachineScheduler pass for this function and target at the current
212 /// optimization level.
214 /// This can also be used to plug a new MachineSchedStrategy into an instance
215 /// of the standard ScheduleDAGMI:
216 /// return new ScheduleDAGMI(C, new MyStrategy(C))
218 /// Return NULL to select the default (generic) machine scheduler.
219 virtual ScheduleDAGInstrs *
220 createMachineScheduler(MachineSchedContext *C) const {
224 /// Similar to createMachineScheduler but used when postRA machine scheduling
226 virtual ScheduleDAGInstrs *
227 createPostMachineScheduler(MachineSchedContext *C) const {
232 // Helper to verify the analysis is really immutable.
233 void setOpt(bool &Opt, bool Val);
235 /// Methods with trivial inline returns are convenient points in the common
236 /// codegen pass pipeline where targets may insert passes. Methods with
237 /// out-of-line standard implementations are major CodeGen stages called by
238 /// addMachinePasses. Some targets may override major stages when inserting
239 /// passes is insufficient, but maintaining overriden stages is more work.
242 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
243 /// passes (which are run just before instruction selector).
244 virtual bool addPreISel() {
248 /// addMachineSSAOptimization - Add standard passes that optimize machine
249 /// instructions in SSA form.
250 virtual void addMachineSSAOptimization();
252 /// Add passes that optimize instruction level parallelism for out-of-order
253 /// targets. These passes are run while the machine code is still in SSA
254 /// form, so they can use MachineTraceMetrics to control their heuristics.
256 /// All passes added here should preserve the MachineDominatorTree,
257 /// MachineLoopInfo, and MachineTraceMetrics analyses.
258 virtual bool addILPOpts() {
262 /// addPreRegAlloc - This method may be implemented by targets that want to
263 /// run passes immediately before register allocation. This should return
264 /// true if -print-machineinstrs should print after these passes.
265 virtual bool addPreRegAlloc() {
269 /// createTargetRegisterAllocator - Create the register allocator pass for
270 /// this target at the current optimization level.
271 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
273 /// addFastRegAlloc - Add the minimum set of target-independent passes that
274 /// are required for fast register allocation.
275 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
277 /// addOptimizedRegAlloc - Add passes related to register allocation.
278 /// LLVMTargetMachine provides standard regalloc passes for most targets.
279 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
281 /// addPreRewrite - Add passes to the optimized register allocation pipeline
282 /// after register allocation is complete, but before virtual registers are
283 /// rewritten to physical registers.
285 /// These passes must preserve VirtRegMap and LiveIntervals, and when running
286 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
287 /// When these passes run, VirtRegMap contains legal physreg assignments for
288 /// all virtual registers.
289 virtual bool addPreRewrite() {
293 /// addPostRegAlloc - This method may be implemented by targets that want to
294 /// run passes after register allocation pass pipeline but before
295 /// prolog-epilog insertion. This should return true if -print-machineinstrs
296 /// should print after these passes.
297 virtual bool addPostRegAlloc() {
301 /// Add passes that optimize machine instructions after register allocation.
302 virtual void addMachineLateOptimization();
304 /// addPreSched2 - This method may be implemented by targets that want to
305 /// run passes after prolog-epilog insertion and before the second instruction
306 /// scheduling pass. This should return true if -print-machineinstrs should
307 /// print after these passes.
308 virtual bool addPreSched2() {
312 /// addGCPasses - Add late codegen passes that analyze code for garbage
313 /// collection. This should return true if GC info should be printed after
315 virtual bool addGCPasses();
317 /// Add standard basic block placement passes.
318 virtual void addBlockPlacement();
320 /// addPreEmitPass - This pass may be implemented by targets that want to run
321 /// passes immediately before machine code is emitted. This should return
322 /// true if -print-machineinstrs should print out the code after the passes.
323 virtual bool addPreEmitPass() {
327 /// Utilities for targets to add passes to the pass manager.
330 /// Add a CodeGen pass at this point in the pipeline after checking overrides.
331 /// Return the pass that was added, or zero if no pass was added.
332 AnalysisID addPass(AnalysisID PassID);
334 /// Add a pass to the PassManager if that pass is supposed to be run, as
335 /// determined by the StartAfter and StopAfter options. Takes ownership of the
337 void addPass(Pass *P);
339 /// addMachinePasses helper to create the target-selected or overriden
341 FunctionPass *createRegAllocPass(bool Optimized);
343 /// printAndVerify - Add a pass to dump then verify the machine function, if
344 /// those steps are enabled.
346 void printAndVerify(const char *Banner);
350 /// List of target independent CodeGen pass IDs.
352 /// \brief Create a basic TargetTransformInfo analysis pass.
354 /// This pass implements the target transform info analysis using the target
355 /// independent information available to the LLVM code generator.
357 createBasicTargetTransformInfoPass(const TargetMachine *TM);
359 /// createUnreachableBlockEliminationPass - The LLVM code generator does not
360 /// work well with unreachable basic blocks (what live ranges make sense for a
361 /// block that cannot be reached?). As such, a code generator should either
362 /// not instruction select unreachable blocks, or run this pass as its
363 /// last LLVM modifying pass to clean up blocks that are not reachable from
365 FunctionPass *createUnreachableBlockEliminationPass();
367 /// MachineFunctionPrinter pass - This pass prints out the machine function to
368 /// the given stream as a debugging tool.
369 MachineFunctionPass *
370 createMachineFunctionPrinterPass(raw_ostream &OS,
371 const std::string &Banner ="");
373 /// MachineLoopInfo - This pass is a loop analysis pass.
374 extern char &MachineLoopInfoID;
376 /// MachineDominators - This pass is a machine dominators analysis pass.
377 extern char &MachineDominatorsID;
379 /// EdgeBundles analysis - Bundle machine CFG edges.
380 extern char &EdgeBundlesID;
382 /// LiveVariables pass - This pass computes the set of blocks in which each
383 /// variable is life and sets machine operand kill flags.
384 extern char &LiveVariablesID;
386 /// PHIElimination - This pass eliminates machine instruction PHI nodes
387 /// by inserting copy instructions. This destroys SSA information, but is the
388 /// desired input for some register allocators. This pass is "required" by
389 /// these register allocator like this: AU.addRequiredID(PHIEliminationID);
390 extern char &PHIEliminationID;
392 /// LiveIntervals - This analysis keeps track of the live ranges of virtual
393 /// and physical registers.
394 extern char &LiveIntervalsID;
396 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
397 extern char &LiveStacksID;
399 /// TwoAddressInstruction - This pass reduces two-address instructions to
400 /// use two operands. This destroys SSA information but it is desired by
401 /// register allocators.
402 extern char &TwoAddressInstructionPassID;
404 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
405 extern char &ProcessImplicitDefsID;
407 /// RegisterCoalescer - This pass merges live ranges to eliminate copies.
408 extern char &RegisterCoalescerID;
410 /// MachineScheduler - This pass schedules machine instructions.
411 extern char &MachineSchedulerID;
413 /// PostMachineScheduler - This pass schedules machine instructions postRA.
414 extern char &PostMachineSchedulerID;
416 /// SpillPlacement analysis. Suggest optimal placement of spill code between
418 extern char &SpillPlacementID;
420 /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as
421 /// assigned in VirtRegMap.
422 extern char &VirtRegRewriterID;
424 /// UnreachableMachineBlockElimination - This pass removes unreachable
425 /// machine basic blocks.
426 extern char &UnreachableMachineBlockElimID;
428 /// DeadMachineInstructionElim - This pass removes dead machine instructions.
429 extern char &DeadMachineInstructionElimID;
431 /// FastRegisterAllocation Pass - This pass register allocates as fast as
432 /// possible. It is best suited for debug code where live ranges are short.
434 FunctionPass *createFastRegisterAllocator();
436 /// BasicRegisterAllocation Pass - This pass implements a degenerate global
437 /// register allocator using the basic regalloc framework.
439 FunctionPass *createBasicRegisterAllocator();
441 /// Greedy register allocation pass - This pass implements a global register
442 /// allocator for optimized builds.
444 FunctionPass *createGreedyRegisterAllocator();
446 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
447 /// Quadratic Prograaming (PBQP) based register allocator.
449 FunctionPass *createDefaultPBQPRegisterAllocator();
451 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
452 /// and eliminates abstract frame references.
453 extern char &PrologEpilogCodeInserterID;
455 /// ExpandPostRAPseudos - This pass expands pseudo instructions after
456 /// register allocation.
457 extern char &ExpandPostRAPseudosID;
459 /// createPostRAScheduler - This pass performs post register allocation
461 extern char &PostRASchedulerID;
463 /// BranchFolding - This pass performs machine code CFG based
464 /// optimizations to delete branches to branches, eliminate branches to
465 /// successor blocks (creating fall throughs), and eliminating branches over
467 extern char &BranchFolderPassID;
469 /// MachineFunctionPrinterPass - This pass prints out MachineInstr's.
470 extern char &MachineFunctionPrinterPassID;
472 /// TailDuplicate - Duplicate blocks with unconditional branches
473 /// into tails of their predecessors.
474 extern char &TailDuplicateID;
476 /// MachineTraceMetrics - This pass computes critical path and CPU resource
477 /// usage in an ensemble of traces.
478 extern char &MachineTraceMetricsID;
480 /// EarlyIfConverter - This pass performs if-conversion on SSA form by
481 /// inserting cmov instructions.
482 extern char &EarlyIfConverterID;
484 /// StackSlotColoring - This pass performs stack coloring and merging.
485 /// It merges disjoint allocas to reduce the stack size.
486 extern char &StackColoringID;
488 /// IfConverter - This pass performs machine code if conversion.
489 extern char &IfConverterID;
491 /// MachineBlockPlacement - This pass places basic blocks based on branch
493 extern char &MachineBlockPlacementID;
495 /// MachineBlockPlacementStats - This pass collects statistics about the
496 /// basic block placement using branch probabilities and block frequency
498 extern char &MachineBlockPlacementStatsID;
500 /// GCLowering Pass - Performs target-independent LLVM IR transformations for
501 /// highly portable strategies.
503 FunctionPass *createGCLoweringPass();
505 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points
506 /// in machine code. Must be added very late during code generation, just
507 /// prior to output, and importantly after all CFG transformations (such as
509 extern char &GCMachineCodeAnalysisID;
511 /// Creates a pass to print GC metadata.
513 FunctionPass *createGCInfoPrinter(raw_ostream &OS);
515 /// MachineCSE - This pass performs global CSE on machine instructions.
516 extern char &MachineCSEID;
518 /// MachineLICM - This pass performs LICM on machine instructions.
519 extern char &MachineLICMID;
521 /// MachineSinking - This pass performs sinking on machine instructions.
522 extern char &MachineSinkingID;
524 /// MachineCopyPropagation - This pass performs copy propagation on
525 /// machine instructions.
526 extern char &MachineCopyPropagationID;
528 /// PeepholeOptimizer - This pass performs peephole optimizations -
529 /// like extension and comparison eliminations.
530 extern char &PeepholeOptimizerID;
532 /// OptimizePHIs - This pass optimizes machine instruction PHIs
533 /// to take advantage of opportunities created during DAG legalization.
534 extern char &OptimizePHIsID;
536 /// StackSlotColoring - This pass performs stack slot coloring.
537 extern char &StackSlotColoringID;
539 /// createStackProtectorPass - This pass adds stack protectors to functions.
541 FunctionPass *createStackProtectorPass(const TargetMachine *TM);
543 /// createMachineVerifierPass - This pass verifies cenerated machine code
544 /// instructions for correctness.
546 FunctionPass *createMachineVerifierPass(const char *Banner = 0);
548 /// createDwarfEHPass - This pass mulches exception handling code into a form
549 /// adapted to code generation. Required if using dwarf exception handling.
550 FunctionPass *createDwarfEHPass(const TargetMachine *TM);
552 /// createSjLjEHPreparePass - This pass adapts exception handling code to use
553 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
555 FunctionPass *createSjLjEHPreparePass(const TargetMachine *TM);
557 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack
558 /// slots relative to one another and allocates base registers to access them
559 /// when it is estimated by the target to be out of range of normal frame
560 /// pointer or stack pointer index addressing.
561 extern char &LocalStackSlotAllocationID;
563 /// ExpandISelPseudos - This pass expands pseudo-instructions.
564 extern char &ExpandISelPseudosID;
566 /// createExecutionDependencyFixPass - This pass fixes execution time
567 /// problems with dependent instructions, such as switching execution
568 /// domains to match.
570 /// The pass will examine instructions using and defining registers in RC.
572 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
574 /// UnpackMachineBundles - This pass unpack machine instruction bundles.
575 extern char &UnpackMachineBundlesID;
577 /// FinalizeMachineBundles - This pass finalize machine instruction
578 /// bundles (created earlier, e.g. during pre-RA scheduling).
579 extern char &FinalizeMachineBundlesID;
581 /// StackMapLiveness - This pass analyses the register live-out set of
582 /// stackmap/patchpoint intrinsics and attaches the calculated information to
583 /// the intrinsic for later emission to the StackMap.
584 extern char &StackMapLivenessID;
586 } // End llvm namespace