1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code generation
11 // passes provided by the LLVM backend.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_PASSES_H
16 #define LLVM_CODEGEN_PASSES_H
18 #include "llvm/Pass.h"
19 #include "llvm/Target/TargetMachine.h"
25 class MachineFunctionPass;
28 class ScheduleDAGInstrs;
30 class TargetLoweringBase;
31 class TargetRegisterClass;
33 struct MachineSchedContext;
35 // The old pass manager infrastructure is hidden in a legacy namespace now.
37 class PassManagerBase;
39 using legacy::PassManagerBase;
41 /// Discriminated union of Pass ID types.
43 /// The PassConfig API prefers dealing with IDs because they are safer and more
44 /// efficient. IDs decouple configuration from instantiation. This way, when a
45 /// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to
46 /// refer to a Pass pointer after adding it to a pass manager, which deletes
47 /// redundant pass instances.
49 /// However, it is convient to directly instantiate target passes with
50 /// non-default ctors. These often don't have a registered PassInfo. Rather than
51 /// force all target passes to implement the pass registry boilerplate, allow
52 /// the PassConfig API to handle either type.
54 /// AnalysisID is sadly char*, so PointerIntPair won't work.
55 class IdentifyingPassPtr {
62 IdentifyingPassPtr() : P(nullptr), IsInstance(false) {}
63 IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr), IsInstance(false) {}
64 IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {}
66 bool isValid() const { return P; }
67 bool isInstance() const { return IsInstance; }
69 AnalysisID getID() const {
70 assert(!IsInstance && "Not a Pass ID");
73 Pass *getInstance() const {
74 assert(IsInstance && "Not a Pass Instance");
79 template <> struct isPodLike<IdentifyingPassPtr> {
80 static const bool value = true;
83 /// Target-Independent Code Generator Pass Configuration Options.
85 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
86 /// to the internals of other CodeGen passes.
87 class TargetPassConfig : public ImmutablePass {
89 /// Pseudo Pass IDs. These are defined within TargetPassConfig because they
90 /// are unregistered pass IDs. They are only useful for use with
91 /// TargetPassConfig APIs to identify multiple occurrences of the same pass.
94 /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early
95 /// during codegen, on SSA form.
96 static char EarlyTailDuplicateID;
98 /// PostRAMachineLICM - A clone of the LICM pass that runs during late machine
99 /// optimization after regalloc.
100 static char PostRAMachineLICMID;
104 AnalysisID StartAfter;
105 AnalysisID StopAfter;
108 bool AddingMachinePasses;
112 PassConfigImpl *Impl; // Internal data structures
113 bool Initialized; // Flagged after all passes are configured.
115 // Target Pass Options
116 // Targets provide a default setting, user flags override.
120 /// Default setting for -enable-tail-merge on this target.
121 bool EnableTailMerge;
123 /// Default setting for -enable-shrink-wrap on this target.
124 bool EnableShrinkWrap;
127 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
128 // Dummy constructor.
131 ~TargetPassConfig() override;
135 /// Get the right type of TargetMachine for this target.
136 template<typename TMC> TMC &getTM() const {
137 return *static_cast<TMC*>(TM);
141 void setInitialized() { Initialized = true; }
143 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
145 /// setStartStopPasses - Set the StartAfter and StopAfter passes to allow
146 /// running only a portion of the normal code-gen pass sequence. If the
147 /// Start pass ID is zero, then compilation will begin at the normal point;
148 /// otherwise, clear the Started flag to indicate that passes should not be
149 /// added until the starting pass is seen. If the Stop pass ID is zero,
150 /// then compilation will continue to the end.
151 void setStartStopPasses(AnalysisID Start, AnalysisID Stop) {
154 Started = (StartAfter == nullptr);
157 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
159 bool getEnableTailMerge() const { return EnableTailMerge; }
160 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
162 /// Allow the target to override a specific pass without overriding the pass
163 /// pipeline. When passes are added to the standard pipeline at the
164 /// point where StandardID is expected, add TargetID in its place.
165 void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID);
167 /// Insert InsertedPassID pass after TargetPassID pass.
168 void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID);
170 /// Allow the target to enable a specific standard pass by default.
171 void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
173 /// Allow the target to disable a specific standard pass by default.
174 void disablePass(AnalysisID PassID) {
175 substitutePass(PassID, IdentifyingPassPtr());
178 /// Return the pass substituted for StandardID by the target.
179 /// If no substitution exists, return StandardID.
180 IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const;
182 /// Return true if the optimized regalloc pipeline is enabled.
183 bool getOptimizeRegAlloc() const;
185 /// Return true if shrink wrapping is enabled.
186 bool getEnableShrinkWrap() const;
188 /// Return true if the default global register allocator is in use and
189 /// has not be overriden on the command line with '-regalloc=...'
190 bool usingDefaultRegAlloc() const;
192 /// Add common target configurable passes that perform LLVM IR to IR
193 /// transforms following machine independent optimization.
194 virtual void addIRPasses();
196 /// Add passes to lower exception handling for the code generator.
197 void addPassesToHandleExceptions();
199 /// Add pass to prepare the LLVM IR for code generation. This should be done
200 /// before exception handling preparation passes.
201 virtual void addCodeGenPrepare();
203 /// Add common passes that perform LLVM IR to IR transforms in preparation for
204 /// instruction selection.
205 virtual void addISelPrepare();
207 /// addInstSelector - This method should install an instruction selector pass,
208 /// which converts from LLVM code to machine instructions.
209 virtual bool addInstSelector() {
213 /// Add the complete, standard set of LLVM CodeGen passes.
214 /// Fully developed targets will not generally override this.
215 virtual void addMachinePasses();
217 /// Create an instance of ScheduleDAGInstrs to be run within the standard
218 /// MachineScheduler pass for this function and target at the current
219 /// optimization level.
221 /// This can also be used to plug a new MachineSchedStrategy into an instance
222 /// of the standard ScheduleDAGMI:
223 /// return new ScheduleDAGMI(C, make_unique<MyStrategy>(C), /* IsPostRA= */false)
225 /// Return NULL to select the default (generic) machine scheduler.
226 virtual ScheduleDAGInstrs *
227 createMachineScheduler(MachineSchedContext *C) const {
231 /// Similar to createMachineScheduler but used when postRA machine scheduling
233 virtual ScheduleDAGInstrs *
234 createPostMachineScheduler(MachineSchedContext *C) const {
239 // Helper to verify the analysis is really immutable.
240 void setOpt(bool &Opt, bool Val);
242 /// Methods with trivial inline returns are convenient points in the common
243 /// codegen pass pipeline where targets may insert passes. Methods with
244 /// out-of-line standard implementations are major CodeGen stages called by
245 /// addMachinePasses. Some targets may override major stages when inserting
246 /// passes is insufficient, but maintaining overriden stages is more work.
249 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
250 /// passes (which are run just before instruction selector).
251 virtual bool addPreISel() {
255 /// addMachineSSAOptimization - Add standard passes that optimize machine
256 /// instructions in SSA form.
257 virtual void addMachineSSAOptimization();
259 /// Add passes that optimize instruction level parallelism for out-of-order
260 /// targets. These passes are run while the machine code is still in SSA
261 /// form, so they can use MachineTraceMetrics to control their heuristics.
263 /// All passes added here should preserve the MachineDominatorTree,
264 /// MachineLoopInfo, and MachineTraceMetrics analyses.
265 virtual bool addILPOpts() {
269 /// This method may be implemented by targets that want to run passes
270 /// immediately before register allocation.
271 virtual void addPreRegAlloc() { }
273 /// createTargetRegisterAllocator - Create the register allocator pass for
274 /// this target at the current optimization level.
275 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
277 /// addFastRegAlloc - Add the minimum set of target-independent passes that
278 /// are required for fast register allocation.
279 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
281 /// addOptimizedRegAlloc - Add passes related to register allocation.
282 /// LLVMTargetMachine provides standard regalloc passes for most targets.
283 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
285 /// addPreRewrite - Add passes to the optimized register allocation pipeline
286 /// after register allocation is complete, but before virtual registers are
287 /// rewritten to physical registers.
289 /// These passes must preserve VirtRegMap and LiveIntervals, and when running
290 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
291 /// When these passes run, VirtRegMap contains legal physreg assignments for
292 /// all virtual registers.
293 virtual bool addPreRewrite() {
297 /// This method may be implemented by targets that want to run passes after
298 /// register allocation pass pipeline but before prolog-epilog insertion.
299 virtual void addPostRegAlloc() { }
301 /// Add passes that optimize machine instructions after register allocation.
302 virtual void addMachineLateOptimization();
304 /// This method may be implemented by targets that want to run passes after
305 /// prolog-epilog insertion and before the second instruction scheduling pass.
306 virtual void addPreSched2() { }
308 /// addGCPasses - Add late codegen passes that analyze code for garbage
309 /// collection. This should return true if GC info should be printed after
311 virtual bool addGCPasses();
313 /// Add standard basic block placement passes.
314 virtual void addBlockPlacement();
316 /// This pass may be implemented by targets that want to run passes
317 /// immediately before machine code is emitted.
318 virtual void addPreEmitPass() { }
320 /// Utilities for targets to add passes to the pass manager.
323 /// Add a CodeGen pass at this point in the pipeline after checking overrides.
324 /// Return the pass that was added, or zero if no pass was added.
325 /// @p printAfter if true and adding a machine function pass add an extra
326 /// machine printer pass afterwards
327 /// @p verifyAfter if true and adding a machine function pass add an extra
328 /// machine verification pass afterwards.
329 AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true,
330 bool printAfter = true);
332 /// Add a pass to the PassManager if that pass is supposed to be run, as
333 /// determined by the StartAfter and StopAfter options. Takes ownership of the
335 /// @p printAfter if true and adding a machine function pass add an extra
336 /// machine printer pass afterwards
337 /// @p verifyAfter if true and adding a machine function pass add an extra
338 /// machine verification pass afterwards.
339 void addPass(Pass *P, bool verifyAfter = true, bool printAfter = true);
341 /// addMachinePasses helper to create the target-selected or overriden
343 FunctionPass *createRegAllocPass(bool Optimized);
345 /// printAndVerify - Add a pass to dump then verify the machine function, if
346 /// those steps are enabled.
348 void printAndVerify(const std::string &Banner);
350 /// Add a pass to print the machine function if printing is enabled.
351 void addPrintPass(const std::string &Banner);
353 /// Add a pass to perform basic verification of the machine function if
354 /// verification is enabled.
355 void addVerifyPass(const std::string &Banner);
359 /// List of target independent CodeGen pass IDs.
361 FunctionPass *createAtomicExpandPass(const TargetMachine *TM);
363 /// createUnreachableBlockEliminationPass - The LLVM code generator does not
364 /// work well with unreachable basic blocks (what live ranges make sense for a
365 /// block that cannot be reached?). As such, a code generator should either
366 /// not instruction select unreachable blocks, or run this pass as its
367 /// last LLVM modifying pass to clean up blocks that are not reachable from
369 FunctionPass *createUnreachableBlockEliminationPass();
371 /// MachineFunctionPrinter pass - This pass prints out the machine function to
372 /// the given stream as a debugging tool.
373 MachineFunctionPass *
374 createMachineFunctionPrinterPass(raw_ostream &OS,
375 const std::string &Banner ="");
377 /// MIRPrinting pass - this pass prints out the LLVM IR into the given stream
378 /// using the MIR serialization format.
379 MachineFunctionPass *createPrintMIRPass(raw_ostream &OS);
381 /// createCodeGenPreparePass - Transform the code to expose more pattern
382 /// matching during instruction selection.
383 FunctionPass *createCodeGenPreparePass(const TargetMachine *TM = nullptr);
385 /// AtomicExpandID -- Lowers atomic operations in terms of either cmpxchg
386 /// load-linked/store-conditional loops.
387 extern char &AtomicExpandID;
389 /// MachineLoopInfo - This pass is a loop analysis pass.
390 extern char &MachineLoopInfoID;
392 /// MachineDominators - This pass is a machine dominators analysis pass.
393 extern char &MachineDominatorsID;
395 /// MachineDominanaceFrontier - This pass is a machine dominators analysis pass.
396 extern char &MachineDominanceFrontierID;
398 /// EdgeBundles analysis - Bundle machine CFG edges.
399 extern char &EdgeBundlesID;
401 /// LiveVariables pass - This pass computes the set of blocks in which each
402 /// variable is life and sets machine operand kill flags.
403 extern char &LiveVariablesID;
405 /// PHIElimination - This pass eliminates machine instruction PHI nodes
406 /// by inserting copy instructions. This destroys SSA information, but is the
407 /// desired input for some register allocators. This pass is "required" by
408 /// these register allocator like this: AU.addRequiredID(PHIEliminationID);
409 extern char &PHIEliminationID;
411 /// LiveIntervals - This analysis keeps track of the live ranges of virtual
412 /// and physical registers.
413 extern char &LiveIntervalsID;
415 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
416 extern char &LiveStacksID;
418 /// TwoAddressInstruction - This pass reduces two-address instructions to
419 /// use two operands. This destroys SSA information but it is desired by
420 /// register allocators.
421 extern char &TwoAddressInstructionPassID;
423 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
424 extern char &ProcessImplicitDefsID;
426 /// RegisterCoalescer - This pass merges live ranges to eliminate copies.
427 extern char &RegisterCoalescerID;
429 /// MachineScheduler - This pass schedules machine instructions.
430 extern char &MachineSchedulerID;
432 /// PostMachineScheduler - This pass schedules machine instructions postRA.
433 extern char &PostMachineSchedulerID;
435 /// SpillPlacement analysis. Suggest optimal placement of spill code between
437 extern char &SpillPlacementID;
439 /// ShrinkWrap pass. Look for the best place to insert save and restore
440 // instruction and update the MachineFunctionInfo with that information.
441 extern char &ShrinkWrapID;
443 /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as
444 /// assigned in VirtRegMap.
445 extern char &VirtRegRewriterID;
447 /// UnreachableMachineBlockElimination - This pass removes unreachable
448 /// machine basic blocks.
449 extern char &UnreachableMachineBlockElimID;
451 /// DeadMachineInstructionElim - This pass removes dead machine instructions.
452 extern char &DeadMachineInstructionElimID;
454 /// FastRegisterAllocation Pass - This pass register allocates as fast as
455 /// possible. It is best suited for debug code where live ranges are short.
457 FunctionPass *createFastRegisterAllocator();
459 /// BasicRegisterAllocation Pass - This pass implements a degenerate global
460 /// register allocator using the basic regalloc framework.
462 FunctionPass *createBasicRegisterAllocator();
464 /// Greedy register allocation pass - This pass implements a global register
465 /// allocator for optimized builds.
467 FunctionPass *createGreedyRegisterAllocator();
469 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
470 /// Quadratic Prograaming (PBQP) based register allocator.
472 FunctionPass *createDefaultPBQPRegisterAllocator();
474 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
475 /// and eliminates abstract frame references.
476 extern char &PrologEpilogCodeInserterID;
478 /// ExpandPostRAPseudos - This pass expands pseudo instructions after
479 /// register allocation.
480 extern char &ExpandPostRAPseudosID;
482 /// createPostRAScheduler - This pass performs post register allocation
484 extern char &PostRASchedulerID;
486 /// BranchFolding - This pass performs machine code CFG based
487 /// optimizations to delete branches to branches, eliminate branches to
488 /// successor blocks (creating fall throughs), and eliminating branches over
490 extern char &BranchFolderPassID;
492 /// MachineFunctionPrinterPass - This pass prints out MachineInstr's.
493 extern char &MachineFunctionPrinterPassID;
495 /// MIRPrintingPass - this pass prints out the LLVM IR using the MIR
496 /// serialization format.
497 extern char &MIRPrintingPassID;
499 /// TailDuplicate - Duplicate blocks with unconditional branches
500 /// into tails of their predecessors.
501 extern char &TailDuplicateID;
503 /// MachineTraceMetrics - This pass computes critical path and CPU resource
504 /// usage in an ensemble of traces.
505 extern char &MachineTraceMetricsID;
507 /// EarlyIfConverter - This pass performs if-conversion on SSA form by
508 /// inserting cmov instructions.
509 extern char &EarlyIfConverterID;
511 /// This pass performs instruction combining using trace metrics to estimate
512 /// critical-path and resource depth.
513 extern char &MachineCombinerID;
515 /// StackSlotColoring - This pass performs stack coloring and merging.
516 /// It merges disjoint allocas to reduce the stack size.
517 extern char &StackColoringID;
519 /// IfConverter - This pass performs machine code if conversion.
520 extern char &IfConverterID;
522 FunctionPass *createIfConverter(std::function<bool(const Function &)> Ftor);
524 /// MachineBlockPlacement - This pass places basic blocks based on branch
526 extern char &MachineBlockPlacementID;
528 /// MachineBlockPlacementStats - This pass collects statistics about the
529 /// basic block placement using branch probabilities and block frequency
531 extern char &MachineBlockPlacementStatsID;
533 /// GCLowering Pass - Used by gc.root to perform its default lowering
535 FunctionPass *createGCLoweringPass();
537 /// ShadowStackGCLowering - Implements the custom lowering mechanism
538 /// used by the shadow stack GC. Only runs on functions which opt in to
539 /// the shadow stack collector.
540 FunctionPass *createShadowStackGCLoweringPass();
542 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points
543 /// in machine code. Must be added very late during code generation, just
544 /// prior to output, and importantly after all CFG transformations (such as
546 extern char &GCMachineCodeAnalysisID;
548 /// Creates a pass to print GC metadata.
550 FunctionPass *createGCInfoPrinter(raw_ostream &OS);
552 /// MachineCSE - This pass performs global CSE on machine instructions.
553 extern char &MachineCSEID;
555 /// ImplicitNullChecks - This pass folds null pointer checks into nearby
556 /// memory operations.
557 extern char &ImplicitNullChecksID;
559 /// MachineLICM - This pass performs LICM on machine instructions.
560 extern char &MachineLICMID;
562 /// MachineSinking - This pass performs sinking on machine instructions.
563 extern char &MachineSinkingID;
565 /// MachineCopyPropagation - This pass performs copy propagation on
566 /// machine instructions.
567 extern char &MachineCopyPropagationID;
569 /// PeepholeOptimizer - This pass performs peephole optimizations -
570 /// like extension and comparison eliminations.
571 extern char &PeepholeOptimizerID;
573 /// OptimizePHIs - This pass optimizes machine instruction PHIs
574 /// to take advantage of opportunities created during DAG legalization.
575 extern char &OptimizePHIsID;
577 /// StackSlotColoring - This pass performs stack slot coloring.
578 extern char &StackSlotColoringID;
580 /// createStackProtectorPass - This pass adds stack protectors to functions.
582 FunctionPass *createStackProtectorPass(const TargetMachine *TM);
584 /// createMachineVerifierPass - This pass verifies cenerated machine code
585 /// instructions for correctness.
587 FunctionPass *createMachineVerifierPass(const std::string& Banner);
589 /// createDwarfEHPass - This pass mulches exception handling code into a form
590 /// adapted to code generation. Required if using dwarf exception handling.
591 FunctionPass *createDwarfEHPass(const TargetMachine *TM);
593 /// createWinEHPass - Prepares personality functions used by MSVC on Windows,
594 /// in addition to the Itanium LSDA based personalities.
595 FunctionPass *createWinEHPass(const TargetMachine *TM);
597 /// createSjLjEHPreparePass - This pass adapts exception handling code to use
598 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
600 FunctionPass *createSjLjEHPreparePass(const TargetMachine *TM);
602 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack
603 /// slots relative to one another and allocates base registers to access them
604 /// when it is estimated by the target to be out of range of normal frame
605 /// pointer or stack pointer index addressing.
606 extern char &LocalStackSlotAllocationID;
608 /// ExpandISelPseudos - This pass expands pseudo-instructions.
609 extern char &ExpandISelPseudosID;
611 /// createExecutionDependencyFixPass - This pass fixes execution time
612 /// problems with dependent instructions, such as switching execution
613 /// domains to match.
615 /// The pass will examine instructions using and defining registers in RC.
617 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
619 /// UnpackMachineBundles - This pass unpack machine instruction bundles.
620 extern char &UnpackMachineBundlesID;
623 createUnpackMachineBundles(std::function<bool(const Function &)> Ftor);
625 /// FinalizeMachineBundles - This pass finalize machine instruction
626 /// bundles (created earlier, e.g. during pre-RA scheduling).
627 extern char &FinalizeMachineBundlesID;
629 /// StackMapLiveness - This pass analyses the register live-out set of
630 /// stackmap/patchpoint intrinsics and attaches the calculated information to
631 /// the intrinsic for later emission to the StackMap.
632 extern char &StackMapLivenessID;
634 /// createJumpInstrTables - This pass creates jump-instruction tables.
635 ModulePass *createJumpInstrTablesPass();
637 /// createForwardControlFlowIntegrityPass - This pass adds control-flow
639 ModulePass *createForwardControlFlowIntegrityPass();
641 /// InterleavedAccess Pass - This pass identifies and matches interleaved
642 /// memory accesses to target specific intrinsics.
644 FunctionPass *createInterleavedAccessPass(const TargetMachine *TM);
645 } // End llvm namespace
647 /// Target machine pass initializer for passes with dependencies. Use with
648 /// INITIALIZE_TM_PASS_END.
649 #define INITIALIZE_TM_PASS_BEGIN INITIALIZE_PASS_BEGIN
651 /// Target machine pass initializer for passes with dependencies. Use with
652 /// INITIALIZE_TM_PASS_BEGIN.
653 #define INITIALIZE_TM_PASS_END(passName, arg, name, cfg, analysis) \
654 PassInfo *PI = new PassInfo(name, arg, & passName ::ID, \
655 PassInfo::NormalCtor_t(callDefaultCtor< passName >), cfg, analysis, \
656 PassInfo::TargetMachineCtor_t(callTargetMachineCtor< passName >)); \
657 Registry.registerPass(*PI, true); \
660 void llvm::initialize##passName##Pass(PassRegistry &Registry) { \
661 CALL_ONCE_INITIALIZATION(initialize##passName##PassOnce) \
664 /// This initializer registers TargetMachine constructor, so the pass being
665 /// initialized can use target dependent interfaces. Please do not move this
666 /// macro to be together with INITIALIZE_PASS, which is a complete target
667 /// independent initializer, and we don't want to make libScalarOpts depend
669 #define INITIALIZE_TM_PASS(passName, arg, name, cfg, analysis) \
670 INITIALIZE_TM_PASS_BEGIN(passName, arg, name, cfg, analysis) \
671 INITIALIZE_TM_PASS_END(passName, arg, name, cfg, analysis)