1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code generation
11 // passes provided by the LLVM backend.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_PASSES_H
16 #define LLVM_CODEGEN_PASSES_H
18 #include "llvm/Pass.h"
19 #include "llvm/Target/TargetMachine.h"
25 class MachineFunctionPass;
27 class PassManagerBase;
28 class TargetLoweringBase;
30 class TargetRegisterClass;
38 /// Target-Independent Code Generator Pass Configuration Options.
40 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
41 /// to the internals of other CodeGen passes.
42 class TargetPassConfig : public ImmutablePass {
44 /// Pseudo Pass IDs. These are defined within TargetPassConfig because they
45 /// are unregistered pass IDs. They are only useful for use with
46 /// TargetPassConfig APIs to identify multiple occurrences of the same pass.
49 /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early
50 /// during codegen, on SSA form.
51 static char EarlyTailDuplicateID;
53 /// PostRAMachineLICM - A clone of the LICM pass that runs during late machine
54 /// optimization after regalloc.
55 static char PostRAMachineLICMID;
59 AnalysisID StartAfter;
66 PassConfigImpl *Impl; // Internal data structures
67 bool Initialized; // Flagged after all passes are configured.
69 // Target Pass Options
70 // Targets provide a default setting, user flags override.
74 /// Default setting for -enable-tail-merge on this target.
78 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
82 virtual ~TargetPassConfig();
86 /// Get the right type of TargetMachine for this target.
87 template<typename TMC> TMC &getTM() const {
88 return *static_cast<TMC*>(TM);
91 const TargetLowering *getTargetLowering() const {
92 return TM->getTargetLowering();
96 void setInitialized() { Initialized = true; }
98 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
100 /// setStartStopPasses - Set the StartAfter and StopAfter passes to allow
101 /// running only a portion of the normal code-gen pass sequence. If the
102 /// Start pass ID is zero, then compilation will begin at the normal point;
103 /// otherwise, clear the Started flag to indicate that passes should not be
104 /// added until the starting pass is seen. If the Stop pass ID is zero,
105 /// then compilation will continue to the end.
106 void setStartStopPasses(AnalysisID Start, AnalysisID Stop) {
109 Started = (StartAfter == 0);
112 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
114 bool getEnableTailMerge() const { return EnableTailMerge; }
115 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
117 /// Allow the target to override a specific pass without overriding the pass
118 /// pipeline. When passes are added to the standard pipeline at the
119 /// point where StandardID is expected, add TargetID in its place.
120 void substitutePass(AnalysisID StandardID, AnalysisID TargetID);
122 /// Insert InsertedPassID pass after TargetPassID pass.
123 void insertPass(AnalysisID TargetPassID, AnalysisID InsertedPassID);
125 /// Allow the target to enable a specific standard pass by default.
126 void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
128 /// Allow the target to disable a specific standard pass by default.
129 void disablePass(AnalysisID PassID) { substitutePass(PassID, 0); }
131 /// Return the pass substituted for StandardID by the target.
132 /// If no substitution exists, return StandardID.
133 AnalysisID getPassSubstitution(AnalysisID StandardID) const;
135 /// Return true if the optimized regalloc pipeline is enabled.
136 bool getOptimizeRegAlloc() const;
138 /// Add common target configurable passes that perform LLVM IR to IR
139 /// transforms following machine independent optimization.
140 virtual void addIRPasses();
142 /// Add passes to lower exception handling for the code generator.
143 void addPassesToHandleExceptions();
145 /// Add pass to prepare the LLVM IR for code generation. This should be done
146 /// before exception handling preparation passes.
147 virtual void addCodeGenPrepare();
149 /// Add common passes that perform LLVM IR to IR transforms in preparation for
150 /// instruction selection.
151 virtual void addISelPrepare();
153 /// addInstSelector - This method should install an instruction selector pass,
154 /// which converts from LLVM code to machine instructions.
155 virtual bool addInstSelector() {
159 /// Add the complete, standard set of LLVM CodeGen passes.
160 /// Fully developed targets will not generally override this.
161 virtual void addMachinePasses();
164 // Helper to verify the analysis is really immutable.
165 void setOpt(bool &Opt, bool Val);
167 /// Methods with trivial inline returns are convenient points in the common
168 /// codegen pass pipeline where targets may insert passes. Methods with
169 /// out-of-line standard implementations are major CodeGen stages called by
170 /// addMachinePasses. Some targets may override major stages when inserting
171 /// passes is insufficient, but maintaining overriden stages is more work.
174 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
175 /// passes (which are run just before instruction selector).
176 virtual bool addPreISel() {
180 /// addMachineSSAOptimization - Add standard passes that optimize machine
181 /// instructions in SSA form.
182 virtual void addMachineSSAOptimization();
184 /// Add passes that optimize instruction level parallelism for out-of-order
185 /// targets. These passes are run while the machine code is still in SSA
186 /// form, so they can use MachineTraceMetrics to control their heuristics.
188 /// All passes added here should preserve the MachineDominatorTree,
189 /// MachineLoopInfo, and MachineTraceMetrics analyses.
190 virtual bool addILPOpts() {
194 /// addPreRegAlloc - This method may be implemented by targets that want to
195 /// run passes immediately before register allocation. This should return
196 /// true if -print-machineinstrs should print after these passes.
197 virtual bool addPreRegAlloc() {
201 /// createTargetRegisterAllocator - Create the register allocator pass for
202 /// this target at the current optimization level.
203 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
205 /// addFastRegAlloc - Add the minimum set of target-independent passes that
206 /// are required for fast register allocation.
207 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
209 /// addOptimizedRegAlloc - Add passes related to register allocation.
210 /// LLVMTargetMachine provides standard regalloc passes for most targets.
211 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
213 /// addPreRewrite - Add passes to the optimized register allocation pipeline
214 /// after register allocation is complete, but before virtual registers are
215 /// rewritten to physical registers.
217 /// These passes must preserve VirtRegMap and LiveIntervals, and when running
218 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
219 /// When these passes run, VirtRegMap contains legal physreg assignments for
220 /// all virtual registers.
221 virtual bool addPreRewrite() {
225 /// addFinalizeRegAlloc - This method may be implemented by targets that want
226 /// to run passes within the regalloc pipeline, immediately after the register
227 /// allocation pass itself. These passes run as soon as virtual regisiters
228 /// have been rewritten to physical registers but before and other postRA
229 /// optimization happens. Targets that have marked instructions for bundling
230 /// must have finalized those bundles by the time these passes have run,
231 /// because subsequent passes are not guaranteed to be bundle-aware.
232 virtual bool addFinalizeRegAlloc() {
236 /// addPostRegAlloc - This method may be implemented by targets that want to
237 /// run passes after register allocation pass pipeline but before
238 /// prolog-epilog insertion. This should return true if -print-machineinstrs
239 /// should print after these passes.
240 virtual bool addPostRegAlloc() {
244 /// Add passes that optimize machine instructions after register allocation.
245 virtual void addMachineLateOptimization();
247 /// addPreSched2 - This method may be implemented by targets that want to
248 /// run passes after prolog-epilog insertion and before the second instruction
249 /// scheduling pass. This should return true if -print-machineinstrs should
250 /// print after these passes.
251 virtual bool addPreSched2() {
255 /// addGCPasses - Add late codegen passes that analyze code for garbage
256 /// collection. This should return true if GC info should be printed after
258 virtual bool addGCPasses();
260 /// Add standard basic block placement passes.
261 virtual void addBlockPlacement();
263 /// addPreEmitPass - This pass may be implemented by targets that want to run
264 /// passes immediately before machine code is emitted. This should return
265 /// true if -print-machineinstrs should print out the code after the passes.
266 virtual bool addPreEmitPass() {
270 /// Utilities for targets to add passes to the pass manager.
273 /// Add a CodeGen pass at this point in the pipeline after checking overrides.
274 /// Return the pass that was added, or zero if no pass was added.
275 AnalysisID addPass(AnalysisID PassID);
277 /// Add a pass to the PassManager if that pass is supposed to be run, as
278 /// determined by the StartAfter and StopAfter options.
279 void addPass(Pass *P);
281 /// addMachinePasses helper to create the target-selected or overriden
283 FunctionPass *createRegAllocPass(bool Optimized);
285 /// printAndVerify - Add a pass to dump then verify the machine function, if
286 /// those steps are enabled.
288 void printAndVerify(const char *Banner);
292 /// List of target independent CodeGen pass IDs.
294 /// \brief Create a basic TargetTransformInfo analysis pass.
296 /// This pass implements the target transform info analysis using the target
297 /// independent information available to the LLVM code generator.
299 createBasicTargetTransformInfoPass(const TargetLoweringBase *TLI);
301 /// createUnreachableBlockEliminationPass - The LLVM code generator does not
302 /// work well with unreachable basic blocks (what live ranges make sense for a
303 /// block that cannot be reached?). As such, a code generator should either
304 /// not instruction select unreachable blocks, or run this pass as its
305 /// last LLVM modifying pass to clean up blocks that are not reachable from
307 FunctionPass *createUnreachableBlockEliminationPass();
309 /// MachineFunctionPrinter pass - This pass prints out the machine function to
310 /// the given stream as a debugging tool.
311 MachineFunctionPass *
312 createMachineFunctionPrinterPass(raw_ostream &OS,
313 const std::string &Banner ="");
315 /// MachineLoopInfo - This pass is a loop analysis pass.
316 extern char &MachineLoopInfoID;
318 /// MachineDominators - This pass is a machine dominators analysis pass.
319 extern char &MachineDominatorsID;
321 /// EdgeBundles analysis - Bundle machine CFG edges.
322 extern char &EdgeBundlesID;
324 /// LiveVariables pass - This pass computes the set of blocks in which each
325 /// variable is life and sets machine operand kill flags.
326 extern char &LiveVariablesID;
328 /// PHIElimination - This pass eliminates machine instruction PHI nodes
329 /// by inserting copy instructions. This destroys SSA information, but is the
330 /// desired input for some register allocators. This pass is "required" by
331 /// these register allocator like this: AU.addRequiredID(PHIEliminationID);
332 extern char &PHIEliminationID;
334 /// StrongPHIElimination - This pass eliminates machine instruction PHI
335 /// nodes by inserting copy instructions. This destroys SSA information, but
336 /// is the desired input for some register allocators. This pass is
337 /// "required" by these register allocator like this:
338 /// AU.addRequiredID(PHIEliminationID);
339 /// This pass is still in development
340 extern char &StrongPHIEliminationID;
342 /// LiveIntervals - This analysis keeps track of the live ranges of virtual
343 /// and physical registers.
344 extern char &LiveIntervalsID;
346 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
347 extern char &LiveStacksID;
349 /// TwoAddressInstruction - This pass reduces two-address instructions to
350 /// use two operands. This destroys SSA information but it is desired by
351 /// register allocators.
352 extern char &TwoAddressInstructionPassID;
354 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
355 extern char &ProcessImplicitDefsID;
357 /// RegisterCoalescer - This pass merges live ranges to eliminate copies.
358 extern char &RegisterCoalescerID;
360 /// MachineScheduler - This pass schedules machine instructions.
361 extern char &MachineSchedulerID;
363 /// SpillPlacement analysis. Suggest optimal placement of spill code between
365 extern char &SpillPlacementID;
367 /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as
368 /// assigned in VirtRegMap.
369 extern char &VirtRegRewriterID;
371 /// UnreachableMachineBlockElimination - This pass removes unreachable
372 /// machine basic blocks.
373 extern char &UnreachableMachineBlockElimID;
375 /// DeadMachineInstructionElim - This pass removes dead machine instructions.
376 extern char &DeadMachineInstructionElimID;
378 /// FastRegisterAllocation Pass - This pass register allocates as fast as
379 /// possible. It is best suited for debug code where live ranges are short.
381 FunctionPass *createFastRegisterAllocator();
383 /// BasicRegisterAllocation Pass - This pass implements a degenerate global
384 /// register allocator using the basic regalloc framework.
386 FunctionPass *createBasicRegisterAllocator();
388 /// Greedy register allocation pass - This pass implements a global register
389 /// allocator for optimized builds.
391 FunctionPass *createGreedyRegisterAllocator();
393 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
394 /// Quadratic Prograaming (PBQP) based register allocator.
396 FunctionPass *createDefaultPBQPRegisterAllocator();
398 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
399 /// and eliminates abstract frame references.
400 extern char &PrologEpilogCodeInserterID;
402 /// ExpandPostRAPseudos - This pass expands pseudo instructions after
403 /// register allocation.
404 extern char &ExpandPostRAPseudosID;
406 /// createPostRAScheduler - This pass performs post register allocation
408 extern char &PostRASchedulerID;
410 /// BranchFolding - This pass performs machine code CFG based
411 /// optimizations to delete branches to branches, eliminate branches to
412 /// successor blocks (creating fall throughs), and eliminating branches over
414 extern char &BranchFolderPassID;
416 /// MachineFunctionPrinterPass - This pass prints out MachineInstr's.
417 extern char &MachineFunctionPrinterPassID;
419 /// TailDuplicate - Duplicate blocks with unconditional branches
420 /// into tails of their predecessors.
421 extern char &TailDuplicateID;
423 /// MachineTraceMetrics - This pass computes critical path and CPU resource
424 /// usage in an ensemble of traces.
425 extern char &MachineTraceMetricsID;
427 /// EarlyIfConverter - This pass performs if-conversion on SSA form by
428 /// inserting cmov instructions.
429 extern char &EarlyIfConverterID;
431 /// StackSlotColoring - This pass performs stack coloring and merging.
432 /// It merges disjoint allocas to reduce the stack size.
433 extern char &StackColoringID;
435 /// IfConverter - This pass performs machine code if conversion.
436 extern char &IfConverterID;
438 /// MachineBlockPlacement - This pass places basic blocks based on branch
440 extern char &MachineBlockPlacementID;
442 /// MachineBlockPlacementStats - This pass collects statistics about the
443 /// basic block placement using branch probabilities and block frequency
445 extern char &MachineBlockPlacementStatsID;
447 /// Code Placement - This pass optimize code placement and aligns loop
448 /// headers to target specific alignment boundary.
449 extern char &CodePlacementOptID;
451 /// GCLowering Pass - Performs target-independent LLVM IR transformations for
452 /// highly portable strategies.
454 FunctionPass *createGCLoweringPass();
456 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points
457 /// in machine code. Must be added very late during code generation, just
458 /// prior to output, and importantly after all CFG transformations (such as
460 extern char &GCMachineCodeAnalysisID;
462 /// Deleter Pass - Releases GC metadata.
464 FunctionPass *createGCInfoDeleter();
466 /// Creates a pass to print GC metadata.
468 FunctionPass *createGCInfoPrinter(raw_ostream &OS);
470 /// MachineCSE - This pass performs global CSE on machine instructions.
471 extern char &MachineCSEID;
473 /// MachineLICM - This pass performs LICM on machine instructions.
474 extern char &MachineLICMID;
476 /// MachineSinking - This pass performs sinking on machine instructions.
477 extern char &MachineSinkingID;
479 /// MachineCopyPropagation - This pass performs copy propagation on
480 /// machine instructions.
481 extern char &MachineCopyPropagationID;
483 /// PeepholeOptimizer - This pass performs peephole optimizations -
484 /// like extension and comparison eliminations.
485 extern char &PeepholeOptimizerID;
487 /// OptimizePHIs - This pass optimizes machine instruction PHIs
488 /// to take advantage of opportunities created during DAG legalization.
489 extern char &OptimizePHIsID;
491 /// StackSlotColoring - This pass performs stack slot coloring.
492 extern char &StackSlotColoringID;
494 /// createStackProtectorPass - This pass adds stack protectors to functions.
496 FunctionPass *createStackProtectorPass(const TargetLoweringBase *tli);
498 /// createMachineVerifierPass - This pass verifies cenerated machine code
499 /// instructions for correctness.
501 FunctionPass *createMachineVerifierPass(const char *Banner = 0);
503 /// createDwarfEHPass - This pass mulches exception handling code into a form
504 /// adapted to code generation. Required if using dwarf exception handling.
505 FunctionPass *createDwarfEHPass(const TargetMachine *tm);
507 /// createSjLjEHPreparePass - This pass adapts exception handling code to use
508 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
510 FunctionPass *createSjLjEHPreparePass(const TargetLoweringBase *tli);
512 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack
513 /// slots relative to one another and allocates base registers to access them
514 /// when it is estimated by the target to be out of range of normal frame
515 /// pointer or stack pointer index addressing.
516 extern char &LocalStackSlotAllocationID;
518 /// ExpandISelPseudos - This pass expands pseudo-instructions.
519 extern char &ExpandISelPseudosID;
521 /// createExecutionDependencyFixPass - This pass fixes execution time
522 /// problems with dependent instructions, such as switching execution
523 /// domains to match.
525 /// The pass will examine instructions using and defining registers in RC.
527 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
529 /// UnpackMachineBundles - This pass unpack machine instruction bundles.
530 extern char &UnpackMachineBundlesID;
532 /// FinalizeMachineBundles - This pass finalize machine instruction
533 /// bundles (created earlier, e.g. during pre-RA scheduling).
534 extern char &FinalizeMachineBundlesID;
536 } // End llvm namespace