1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code generation
11 // passes provided by the LLVM backend.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_PASSES_H
16 #define LLVM_CODEGEN_PASSES_H
18 #include "llvm/Pass.h"
19 #include "llvm/Target/TargetMachine.h"
24 class MachineFunctionPass;
27 class ScheduleDAGInstrs;
29 class TargetLoweringBase;
30 class TargetRegisterClass;
32 struct MachineSchedContext;
34 // The old pass manager infrastructure is hidden in a legacy namespace now.
36 class PassManagerBase;
38 using legacy::PassManagerBase;
40 /// Discriminated union of Pass ID types.
42 /// The PassConfig API prefers dealing with IDs because they are safer and more
43 /// efficient. IDs decouple configuration from instantiation. This way, when a
44 /// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to
45 /// refer to a Pass pointer after adding it to a pass manager, which deletes
46 /// redundant pass instances.
48 /// However, it is convient to directly instantiate target passes with
49 /// non-default ctors. These often don't have a registered PassInfo. Rather than
50 /// force all target passes to implement the pass registry boilerplate, allow
51 /// the PassConfig API to handle either type.
53 /// AnalysisID is sadly char*, so PointerIntPair won't work.
54 class IdentifyingPassPtr {
61 IdentifyingPassPtr() : P(nullptr), IsInstance(false) {}
62 IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr), IsInstance(false) {}
63 IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {}
65 bool isValid() const { return P; }
66 bool isInstance() const { return IsInstance; }
68 AnalysisID getID() const {
69 assert(!IsInstance && "Not a Pass ID");
72 Pass *getInstance() const {
73 assert(IsInstance && "Not a Pass Instance");
78 template <> struct isPodLike<IdentifyingPassPtr> {
79 static const bool value = true;
82 /// Target-Independent Code Generator Pass Configuration Options.
84 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
85 /// to the internals of other CodeGen passes.
86 class TargetPassConfig : public ImmutablePass {
88 /// Pseudo Pass IDs. These are defined within TargetPassConfig because they
89 /// are unregistered pass IDs. They are only useful for use with
90 /// TargetPassConfig APIs to identify multiple occurrences of the same pass.
93 /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early
94 /// during codegen, on SSA form.
95 static char EarlyTailDuplicateID;
97 /// PostRAMachineLICM - A clone of the LICM pass that runs during late machine
98 /// optimization after regalloc.
99 static char PostRAMachineLICMID;
103 AnalysisID StartAfter;
104 AnalysisID StopAfter;
107 bool AddingMachinePasses;
111 PassConfigImpl *Impl; // Internal data structures
112 bool Initialized; // Flagged after all passes are configured.
114 // Target Pass Options
115 // Targets provide a default setting, user flags override.
119 /// Default setting for -enable-tail-merge on this target.
120 bool EnableTailMerge;
122 /// Default setting for -enable-shrink-wrap on this target.
123 bool EnableShrinkWrap;
126 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
127 // Dummy constructor.
130 ~TargetPassConfig() override;
134 /// Get the right type of TargetMachine for this target.
135 template<typename TMC> TMC &getTM() const {
136 return *static_cast<TMC*>(TM);
140 void setInitialized() { Initialized = true; }
142 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
144 /// setStartStopPasses - Set the StartAfter and StopAfter passes to allow
145 /// running only a portion of the normal code-gen pass sequence. If the
146 /// Start pass ID is zero, then compilation will begin at the normal point;
147 /// otherwise, clear the Started flag to indicate that passes should not be
148 /// added until the starting pass is seen. If the Stop pass ID is zero,
149 /// then compilation will continue to the end.
150 void setStartStopPasses(AnalysisID Start, AnalysisID Stop) {
153 Started = (StartAfter == nullptr);
156 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
158 bool getEnableTailMerge() const { return EnableTailMerge; }
159 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
161 /// Allow the target to override a specific pass without overriding the pass
162 /// pipeline. When passes are added to the standard pipeline at the
163 /// point where StandardID is expected, add TargetID in its place.
164 void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID);
166 /// Insert InsertedPassID pass after TargetPassID pass.
167 void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID);
169 /// Allow the target to enable a specific standard pass by default.
170 void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
172 /// Allow the target to disable a specific standard pass by default.
173 void disablePass(AnalysisID PassID) {
174 substitutePass(PassID, IdentifyingPassPtr());
177 /// Return the pass substituted for StandardID by the target.
178 /// If no substitution exists, return StandardID.
179 IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const;
181 /// Return true if the optimized regalloc pipeline is enabled.
182 bool getOptimizeRegAlloc() const;
184 /// Return true if shrink wrapping is enabled.
185 bool getEnableShrinkWrap() const;
187 /// Return true if the default global register allocator is in use and
188 /// has not be overriden on the command line with '-regalloc=...'
189 bool usingDefaultRegAlloc() const;
191 /// Add common target configurable passes that perform LLVM IR to IR
192 /// transforms following machine independent optimization.
193 virtual void addIRPasses();
195 /// Add passes to lower exception handling for the code generator.
196 void addPassesToHandleExceptions();
198 /// Add pass to prepare the LLVM IR for code generation. This should be done
199 /// before exception handling preparation passes.
200 virtual void addCodeGenPrepare();
202 /// Add common passes that perform LLVM IR to IR transforms in preparation for
203 /// instruction selection.
204 virtual void addISelPrepare();
206 /// addInstSelector - This method should install an instruction selector pass,
207 /// which converts from LLVM code to machine instructions.
208 virtual bool addInstSelector() {
212 /// Add the complete, standard set of LLVM CodeGen passes.
213 /// Fully developed targets will not generally override this.
214 virtual void addMachinePasses();
216 /// Create an instance of ScheduleDAGInstrs to be run within the standard
217 /// MachineScheduler pass for this function and target at the current
218 /// optimization level.
220 /// This can also be used to plug a new MachineSchedStrategy into an instance
221 /// of the standard ScheduleDAGMI:
222 /// return new ScheduleDAGMI(C, make_unique<MyStrategy>(C), /* IsPostRA= */false)
224 /// Return NULL to select the default (generic) machine scheduler.
225 virtual ScheduleDAGInstrs *
226 createMachineScheduler(MachineSchedContext *C) const {
230 /// Similar to createMachineScheduler but used when postRA machine scheduling
232 virtual ScheduleDAGInstrs *
233 createPostMachineScheduler(MachineSchedContext *C) const {
238 // Helper to verify the analysis is really immutable.
239 void setOpt(bool &Opt, bool Val);
241 /// Methods with trivial inline returns are convenient points in the common
242 /// codegen pass pipeline where targets may insert passes. Methods with
243 /// out-of-line standard implementations are major CodeGen stages called by
244 /// addMachinePasses. Some targets may override major stages when inserting
245 /// passes is insufficient, but maintaining overriden stages is more work.
248 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
249 /// passes (which are run just before instruction selector).
250 virtual bool addPreISel() {
254 /// addMachineSSAOptimization - Add standard passes that optimize machine
255 /// instructions in SSA form.
256 virtual void addMachineSSAOptimization();
258 /// Add passes that optimize instruction level parallelism for out-of-order
259 /// targets. These passes are run while the machine code is still in SSA
260 /// form, so they can use MachineTraceMetrics to control their heuristics.
262 /// All passes added here should preserve the MachineDominatorTree,
263 /// MachineLoopInfo, and MachineTraceMetrics analyses.
264 virtual bool addILPOpts() {
268 /// This method may be implemented by targets that want to run passes
269 /// immediately before register allocation.
270 virtual void addPreRegAlloc() { }
272 /// createTargetRegisterAllocator - Create the register allocator pass for
273 /// this target at the current optimization level.
274 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
276 /// addFastRegAlloc - Add the minimum set of target-independent passes that
277 /// are required for fast register allocation.
278 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
280 /// addOptimizedRegAlloc - Add passes related to register allocation.
281 /// LLVMTargetMachine provides standard regalloc passes for most targets.
282 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
284 /// addPreRewrite - Add passes to the optimized register allocation pipeline
285 /// after register allocation is complete, but before virtual registers are
286 /// rewritten to physical registers.
288 /// These passes must preserve VirtRegMap and LiveIntervals, and when running
289 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
290 /// When these passes run, VirtRegMap contains legal physreg assignments for
291 /// all virtual registers.
292 virtual bool addPreRewrite() {
296 /// This method may be implemented by targets that want to run passes after
297 /// register allocation pass pipeline but before prolog-epilog insertion.
298 virtual void addPostRegAlloc() { }
300 /// Add passes that optimize machine instructions after register allocation.
301 virtual void addMachineLateOptimization();
303 /// This method may be implemented by targets that want to run passes after
304 /// prolog-epilog insertion and before the second instruction scheduling pass.
305 virtual void addPreSched2() { }
307 /// addGCPasses - Add late codegen passes that analyze code for garbage
308 /// collection. This should return true if GC info should be printed after
310 virtual bool addGCPasses();
312 /// Add standard basic block placement passes.
313 virtual void addBlockPlacement();
315 /// This pass may be implemented by targets that want to run passes
316 /// immediately before machine code is emitted.
317 virtual void addPreEmitPass() { }
319 /// Utilities for targets to add passes to the pass manager.
322 /// Add a CodeGen pass at this point in the pipeline after checking overrides.
323 /// Return the pass that was added, or zero if no pass was added.
324 /// @p printAfter if true and adding a machine function pass add an extra
325 /// machine printer pass afterwards
326 /// @p verifyAfter if true and adding a machine function pass add an extra
327 /// machine verification pass afterwards.
328 AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true,
329 bool printAfter = true);
331 /// Add a pass to the PassManager if that pass is supposed to be run, as
332 /// determined by the StartAfter and StopAfter options. Takes ownership of the
334 /// @p printAfter if true and adding a machine function pass add an extra
335 /// machine printer pass afterwards
336 /// @p verifyAfter if true and adding a machine function pass add an extra
337 /// machine verification pass afterwards.
338 void addPass(Pass *P, bool verifyAfter = true, bool printAfter = true);
340 /// addMachinePasses helper to create the target-selected or overriden
342 FunctionPass *createRegAllocPass(bool Optimized);
344 /// printAndVerify - Add a pass to dump then verify the machine function, if
345 /// those steps are enabled.
347 void printAndVerify(const std::string &Banner);
349 /// Add a pass to print the machine function if printing is enabled.
350 void addPrintPass(const std::string &Banner);
352 /// Add a pass to perform basic verification of the machine function if
353 /// verification is enabled.
354 void addVerifyPass(const std::string &Banner);
358 /// List of target independent CodeGen pass IDs.
360 FunctionPass *createAtomicExpandPass(const TargetMachine *TM);
362 /// createUnreachableBlockEliminationPass - The LLVM code generator does not
363 /// work well with unreachable basic blocks (what live ranges make sense for a
364 /// block that cannot be reached?). As such, a code generator should either
365 /// not instruction select unreachable blocks, or run this pass as its
366 /// last LLVM modifying pass to clean up blocks that are not reachable from
368 FunctionPass *createUnreachableBlockEliminationPass();
370 /// MachineFunctionPrinter pass - This pass prints out the machine function to
371 /// the given stream as a debugging tool.
372 MachineFunctionPass *
373 createMachineFunctionPrinterPass(raw_ostream &OS,
374 const std::string &Banner ="");
376 /// MIRPrinting pass - this pass prints out the LLVM IR into the given stream
377 /// using the MIR serialization format.
378 MachineFunctionPass *createPrintMIRPass(raw_ostream &OS);
380 /// createCodeGenPreparePass - Transform the code to expose more pattern
381 /// matching during instruction selection.
382 FunctionPass *createCodeGenPreparePass(const TargetMachine *TM = nullptr);
384 /// AtomicExpandID -- Lowers atomic operations in terms of either cmpxchg
385 /// load-linked/store-conditional loops.
386 extern char &AtomicExpandID;
388 /// MachineLoopInfo - This pass is a loop analysis pass.
389 extern char &MachineLoopInfoID;
391 /// MachineDominators - This pass is a machine dominators analysis pass.
392 extern char &MachineDominatorsID;
394 /// MachineDominanaceFrontier - This pass is a machine dominators analysis pass.
395 extern char &MachineDominanceFrontierID;
397 /// EdgeBundles analysis - Bundle machine CFG edges.
398 extern char &EdgeBundlesID;
400 /// LiveVariables pass - This pass computes the set of blocks in which each
401 /// variable is life and sets machine operand kill flags.
402 extern char &LiveVariablesID;
404 /// PHIElimination - This pass eliminates machine instruction PHI nodes
405 /// by inserting copy instructions. This destroys SSA information, but is the
406 /// desired input for some register allocators. This pass is "required" by
407 /// these register allocator like this: AU.addRequiredID(PHIEliminationID);
408 extern char &PHIEliminationID;
410 /// LiveIntervals - This analysis keeps track of the live ranges of virtual
411 /// and physical registers.
412 extern char &LiveIntervalsID;
414 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
415 extern char &LiveStacksID;
417 /// TwoAddressInstruction - This pass reduces two-address instructions to
418 /// use two operands. This destroys SSA information but it is desired by
419 /// register allocators.
420 extern char &TwoAddressInstructionPassID;
422 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
423 extern char &ProcessImplicitDefsID;
425 /// RegisterCoalescer - This pass merges live ranges to eliminate copies.
426 extern char &RegisterCoalescerID;
428 /// MachineScheduler - This pass schedules machine instructions.
429 extern char &MachineSchedulerID;
431 /// PostMachineScheduler - This pass schedules machine instructions postRA.
432 extern char &PostMachineSchedulerID;
434 /// SpillPlacement analysis. Suggest optimal placement of spill code between
436 extern char &SpillPlacementID;
438 /// ShrinkWrap pass. Look for the best place to insert save and restore
439 // instruction and update the MachineFunctionInfo with that information.
440 extern char &ShrinkWrapID;
442 /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as
443 /// assigned in VirtRegMap.
444 extern char &VirtRegRewriterID;
446 /// UnreachableMachineBlockElimination - This pass removes unreachable
447 /// machine basic blocks.
448 extern char &UnreachableMachineBlockElimID;
450 /// DeadMachineInstructionElim - This pass removes dead machine instructions.
451 extern char &DeadMachineInstructionElimID;
453 /// FastRegisterAllocation Pass - This pass register allocates as fast as
454 /// possible. It is best suited for debug code where live ranges are short.
456 FunctionPass *createFastRegisterAllocator();
458 /// BasicRegisterAllocation Pass - This pass implements a degenerate global
459 /// register allocator using the basic regalloc framework.
461 FunctionPass *createBasicRegisterAllocator();
463 /// Greedy register allocation pass - This pass implements a global register
464 /// allocator for optimized builds.
466 FunctionPass *createGreedyRegisterAllocator();
468 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
469 /// Quadratic Prograaming (PBQP) based register allocator.
471 FunctionPass *createDefaultPBQPRegisterAllocator();
473 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
474 /// and eliminates abstract frame references.
475 extern char &PrologEpilogCodeInserterID;
477 /// ExpandPostRAPseudos - This pass expands pseudo instructions after
478 /// register allocation.
479 extern char &ExpandPostRAPseudosID;
481 /// createPostRAScheduler - This pass performs post register allocation
483 extern char &PostRASchedulerID;
485 /// BranchFolding - This pass performs machine code CFG based
486 /// optimizations to delete branches to branches, eliminate branches to
487 /// successor blocks (creating fall throughs), and eliminating branches over
489 extern char &BranchFolderPassID;
491 /// MachineFunctionPrinterPass - This pass prints out MachineInstr's.
492 extern char &MachineFunctionPrinterPassID;
494 /// MIRPrintingPass - this pass prints out the LLVM IR using the MIR
495 /// serialization format.
496 extern char &MIRPrintingPassID;
498 /// TailDuplicate - Duplicate blocks with unconditional branches
499 /// into tails of their predecessors.
500 extern char &TailDuplicateID;
502 /// MachineTraceMetrics - This pass computes critical path and CPU resource
503 /// usage in an ensemble of traces.
504 extern char &MachineTraceMetricsID;
506 /// EarlyIfConverter - This pass performs if-conversion on SSA form by
507 /// inserting cmov instructions.
508 extern char &EarlyIfConverterID;
510 /// This pass performs instruction combining using trace metrics to estimate
511 /// critical-path and resource depth.
512 extern char &MachineCombinerID;
514 /// StackSlotColoring - This pass performs stack coloring and merging.
515 /// It merges disjoint allocas to reduce the stack size.
516 extern char &StackColoringID;
518 /// IfConverter - This pass performs machine code if conversion.
519 extern char &IfConverterID;
521 FunctionPass *createIfConverter(std::function<bool(const Function &)> Ftor);
523 /// MachineBlockPlacement - This pass places basic blocks based on branch
525 extern char &MachineBlockPlacementID;
527 /// MachineBlockPlacementStats - This pass collects statistics about the
528 /// basic block placement using branch probabilities and block frequency
530 extern char &MachineBlockPlacementStatsID;
532 /// GCLowering Pass - Used by gc.root to perform its default lowering
534 FunctionPass *createGCLoweringPass();
536 /// ShadowStackGCLowering - Implements the custom lowering mechanism
537 /// used by the shadow stack GC. Only runs on functions which opt in to
538 /// the shadow stack collector.
539 FunctionPass *createShadowStackGCLoweringPass();
541 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points
542 /// in machine code. Must be added very late during code generation, just
543 /// prior to output, and importantly after all CFG transformations (such as
545 extern char &GCMachineCodeAnalysisID;
547 /// Creates a pass to print GC metadata.
549 FunctionPass *createGCInfoPrinter(raw_ostream &OS);
551 /// MachineCSE - This pass performs global CSE on machine instructions.
552 extern char &MachineCSEID;
554 /// MachineLICM - This pass performs LICM on machine instructions.
555 extern char &MachineLICMID;
557 /// MachineSinking - This pass performs sinking on machine instructions.
558 extern char &MachineSinkingID;
560 /// MachineCopyPropagation - This pass performs copy propagation on
561 /// machine instructions.
562 extern char &MachineCopyPropagationID;
564 /// PeepholeOptimizer - This pass performs peephole optimizations -
565 /// like extension and comparison eliminations.
566 extern char &PeepholeOptimizerID;
568 /// OptimizePHIs - This pass optimizes machine instruction PHIs
569 /// to take advantage of opportunities created during DAG legalization.
570 extern char &OptimizePHIsID;
572 /// StackSlotColoring - This pass performs stack slot coloring.
573 extern char &StackSlotColoringID;
575 /// createStackProtectorPass - This pass adds stack protectors to functions.
577 FunctionPass *createStackProtectorPass(const TargetMachine *TM);
579 /// createMachineVerifierPass - This pass verifies cenerated machine code
580 /// instructions for correctness.
582 FunctionPass *createMachineVerifierPass(const std::string& Banner);
584 /// createDwarfEHPass - This pass mulches exception handling code into a form
585 /// adapted to code generation. Required if using dwarf exception handling.
586 FunctionPass *createDwarfEHPass(const TargetMachine *TM);
588 /// createWinEHPass - Prepares personality functions used by MSVC on Windows,
589 /// in addition to the Itanium LSDA based personalities.
590 FunctionPass *createWinEHPass(const TargetMachine *TM);
592 /// createSjLjEHPreparePass - This pass adapts exception handling code to use
593 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
595 FunctionPass *createSjLjEHPreparePass(const TargetMachine *TM);
597 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack
598 /// slots relative to one another and allocates base registers to access them
599 /// when it is estimated by the target to be out of range of normal frame
600 /// pointer or stack pointer index addressing.
601 extern char &LocalStackSlotAllocationID;
603 /// ExpandISelPseudos - This pass expands pseudo-instructions.
604 extern char &ExpandISelPseudosID;
606 /// createExecutionDependencyFixPass - This pass fixes execution time
607 /// problems with dependent instructions, such as switching execution
608 /// domains to match.
610 /// The pass will examine instructions using and defining registers in RC.
612 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
614 /// UnpackMachineBundles - This pass unpack machine instruction bundles.
615 extern char &UnpackMachineBundlesID;
618 createUnpackMachineBundles(std::function<bool(const Function &)> Ftor);
620 /// FinalizeMachineBundles - This pass finalize machine instruction
621 /// bundles (created earlier, e.g. during pre-RA scheduling).
622 extern char &FinalizeMachineBundlesID;
624 /// StackMapLiveness - This pass analyses the register live-out set of
625 /// stackmap/patchpoint intrinsics and attaches the calculated information to
626 /// the intrinsic for later emission to the StackMap.
627 extern char &StackMapLivenessID;
629 /// createJumpInstrTables - This pass creates jump-instruction tables.
630 ModulePass *createJumpInstrTablesPass();
632 /// createForwardControlFlowIntegrityPass - This pass adds control-flow
634 ModulePass *createForwardControlFlowIntegrityPass();
635 } // End llvm namespace
637 /// Target machine pass initializer for passes with dependencies. Use with
638 /// INITIALIZE_TM_PASS_END.
639 #define INITIALIZE_TM_PASS_BEGIN INITIALIZE_PASS_BEGIN
641 /// Target machine pass initializer for passes with dependencies. Use with
642 /// INITIALIZE_TM_PASS_BEGIN.
643 #define INITIALIZE_TM_PASS_END(passName, arg, name, cfg, analysis) \
644 PassInfo *PI = new PassInfo(name, arg, & passName ::ID, \
645 PassInfo::NormalCtor_t(callDefaultCtor< passName >), cfg, analysis, \
646 PassInfo::TargetMachineCtor_t(callTargetMachineCtor< passName >)); \
647 Registry.registerPass(*PI, true); \
650 void llvm::initialize##passName##Pass(PassRegistry &Registry) { \
651 CALL_ONCE_INITIALIZATION(initialize##passName##PassOnce) \
654 /// This initializer registers TargetMachine constructor, so the pass being
655 /// initialized can use target dependent interfaces. Please do not move this
656 /// macro to be together with INITIALIZE_PASS, which is a complete target
657 /// independent initializer, and we don't want to make libScalarOpts depend
659 #define INITIALIZE_TM_PASS(passName, arg, name, cfg, analysis) \
660 INITIALIZE_TM_PASS_BEGIN(passName, arg, name, cfg, analysis) \
661 INITIALIZE_TM_PASS_END(passName, arg, name, cfg, analysis)