1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code generation
11 // passes provided by the LLVM backend.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_PASSES_H
16 #define LLVM_CODEGEN_PASSES_H
18 #include "llvm/Pass.h"
19 #include "llvm/Target/TargetMachine.h"
25 class MachineFunctionPass;
28 class TargetRegisterClass;
34 extern char &NoPassID; // Allow targets to choose not to run a pass.
38 /// Target-Independent Code Generator Pass Configuration Options.
40 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
41 /// to the internals of other CodeGen passes.
42 class TargetPassConfig : public ImmutablePass {
44 /// Pseudo Pass IDs. These are defined within TargetPassConfig because they
45 /// are unregistered pass IDs. They are only useful for use with
46 /// TargetPassConfig APIs to identify multiple occurrences of the same pass.
49 /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early
50 /// during codegen, on SSA form.
51 static char EarlyTailDuplicateID;
53 /// PostRAMachineLICM - A clone of the LICM pass that runs during late machine
54 /// optimization after regalloc.
55 static char PostRAMachineLICMID;
60 PassConfigImpl *Impl; // Internal data structures
61 bool Initialized; // Flagged after all passes are configured.
63 // Target Pass Options
64 // Targets provide a default setting, user flags override.
68 /// Default setting for -enable-tail-merge on this target.
72 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
76 virtual ~TargetPassConfig();
80 /// Get the right type of TargetMachine for this target.
81 template<typename TMC> TMC &getTM() const {
82 return *static_cast<TMC*>(TM);
85 const TargetLowering *getTargetLowering() const {
86 return TM->getTargetLowering();
90 void setInitialized() { Initialized = true; }
92 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
94 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
96 bool getEnableTailMerge() const { return EnableTailMerge; }
97 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
99 /// Allow the target to override a specific pass without overriding the pass
100 /// pipeline. When passes are added to the standard pipeline at the
101 /// point where StadardID is expected, add TargetID in its place.
102 void substitutePass(char &StandardID, char &TargetID);
104 /// Allow the target to disable a specific standard pass.
105 void disablePass(char &ID) { substitutePass(ID, NoPassID); }
107 /// Return the pass ssubtituted for StandardID by the target.
108 /// If no substitution exists, return StandardID.
109 AnalysisID getPassSubstitution(AnalysisID StandardID) const;
111 /// Return true if the optimized regalloc pipeline is enabled.
112 bool getOptimizeRegAlloc() const;
114 /// Add common target configurable passes that perform LLVM IR to IR
115 /// transforms following machine independent optimization.
116 virtual void addIRPasses();
118 /// Add common passes that perform LLVM IR to IR transforms in preparation for
119 /// instruction selection.
120 virtual void addISelPrepare();
122 /// addInstSelector - This method should install an instruction selector pass,
123 /// which converts from LLVM code to machine instructions.
124 virtual bool addInstSelector() {
128 /// Add the complete, standard set of LLVM CodeGen passes.
129 /// Fully developed targets will not generally override this.
130 virtual void addMachinePasses();
133 // Helper to verify the analysis is really immutable.
134 void setOpt(bool &Opt, bool Val);
136 /// Methods with trivial inline returns are convenient points in the common
137 /// codegen pass pipeline where targets may insert passes. Methods with
138 /// out-of-line standard implementations are major CodeGen stages called by
139 /// addMachinePasses. Some targets may override major stages when inserting
140 /// passes is insufficient, but maintaining overriden stages is more work.
143 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
144 /// passes (which are run just before instruction selector).
145 virtual bool addPreISel() {
149 /// addMachineSSAOptimization - Add standard passes that optimize machine
150 /// instructions in SSA form.
151 virtual void addMachineSSAOptimization();
153 /// addPreRegAlloc - This method may be implemented by targets that want to
154 /// run passes immediately before register allocation. This should return
155 /// true if -print-machineinstrs should print after these passes.
156 virtual bool addPreRegAlloc() {
160 /// createTargetRegisterAllocator - Create the register allocator pass for
161 /// this target at the current optimization level.
162 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
164 /// addFastRegAlloc - Add the minimum set of target-independent passes that
165 /// are required for fast register allocation.
166 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
168 /// addOptimizedRegAlloc - Add passes related to register allocation.
169 /// LLVMTargetMachine provides standard regalloc passes for most targets.
170 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
172 /// getSchedPass - This method may be implemented by target that want to
173 /// completely override the MachineScheduler pass with a new pass, rather than
174 /// inheriting from ScheduleDAGInstrs.
175 virtual char &getSchedPass() { return NoPassID; }
177 /// addFinalizeRegAlloc - This method may be implemented by targets that want
178 /// to run passes within the regalloc pipeline, immediately after the register
179 /// allocation pass itself. These passes run as soon as virtual regisiters
180 /// have been rewritten to physical registers but before and other postRA
181 /// optimization happens. Targets that have marked instructions for bundling
182 /// must have finalized those bundles by the time these passes have run,
183 /// because subsequent passes are not guaranteed to be bundle-aware.
184 virtual bool addFinalizeRegAlloc() {
188 /// addPostRegAlloc - This method may be implemented by targets that want to
189 /// run passes after register allocation pass pipeline but before
190 /// prolog-epilog insertion. This should return true if -print-machineinstrs
191 /// should print after these passes.
192 virtual bool addPostRegAlloc() {
196 /// Add passes that optimize machine instructions after register allocation.
197 virtual void addMachineLateOptimization();
199 /// addPreSched2 - This method may be implemented by targets that want to
200 /// run passes after prolog-epilog insertion and before the second instruction
201 /// scheduling pass. This should return true if -print-machineinstrs should
202 /// print after these passes.
203 virtual bool addPreSched2() {
207 /// Add standard basic block placement passes.
208 virtual void addBlockPlacement();
210 /// addPreEmitPass - This pass may be implemented by targets that want to run
211 /// passes immediately before machine code is emitted. This should return
212 /// true if -print-machineinstrs should print out the code after the passes.
213 virtual bool addPreEmitPass() {
217 /// Utilities for targets to add passes to the pass manager.
220 /// Add a CodeGen pass at this point in the pipeline after checking overrides.
221 /// Return the pass that was added, or NoPassID.
222 AnalysisID addPass(char &ID);
224 /// addMachinePasses helper to create the target-selected or overriden
226 FunctionPass *createRegAllocPass(bool Optimized);
228 /// printNoVerify - Add a pass to dump the machine function, if debugging is
231 void printNoVerify(const char *Banner) const;
233 /// printAndVerify - Add a pass to dump then verify the machine function, if
234 /// those steps are enabled.
236 void printAndVerify(const char *Banner) const;
240 /// List of target independent CodeGen pass IDs.
242 /// createUnreachableBlockEliminationPass - The LLVM code generator does not
243 /// work well with unreachable basic blocks (what live ranges make sense for a
244 /// block that cannot be reached?). As such, a code generator should either
245 /// not instruction select unreachable blocks, or run this pass as its
246 /// last LLVM modifying pass to clean up blocks that are not reachable from
248 FunctionPass *createUnreachableBlockEliminationPass();
250 /// MachineFunctionPrinter pass - This pass prints out the machine function to
251 /// the given stream as a debugging tool.
252 MachineFunctionPass *
253 createMachineFunctionPrinterPass(raw_ostream &OS,
254 const std::string &Banner ="");
256 /// MachineLoopInfo - This pass is a loop analysis pass.
257 extern char &MachineLoopInfoID;
259 /// MachineLoopRanges - This pass is an on-demand loop coverage analysis.
260 extern char &MachineLoopRangesID;
262 /// MachineDominators - This pass is a machine dominators analysis pass.
263 extern char &MachineDominatorsID;
265 /// EdgeBundles analysis - Bundle machine CFG edges.
266 extern char &EdgeBundlesID;
268 /// LiveVariables pass - This pass computes the set of blocks in which each
269 /// variable is life and sets machine operand kill flags.
270 extern char &LiveVariablesID;
272 /// PHIElimination - This pass eliminates machine instruction PHI nodes
273 /// by inserting copy instructions. This destroys SSA information, but is the
274 /// desired input for some register allocators. This pass is "required" by
275 /// these register allocator like this: AU.addRequiredID(PHIEliminationID);
276 extern char &PHIEliminationID;
278 /// StrongPHIElimination - This pass eliminates machine instruction PHI
279 /// nodes by inserting copy instructions. This destroys SSA information, but
280 /// is the desired input for some register allocators. This pass is
281 /// "required" by these register allocator like this:
282 /// AU.addRequiredID(PHIEliminationID);
283 /// This pass is still in development
284 extern char &StrongPHIEliminationID;
286 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
287 extern char &LiveStacksID;
289 /// TwoAddressInstruction - This pass reduces two-address instructions to
290 /// use two operands. This destroys SSA information but it is desired by
291 /// register allocators.
292 extern char &TwoAddressInstructionPassID;
294 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
295 extern char &ProcessImplicitDefsID;
297 /// RegisterCoalescer - This pass merges live ranges to eliminate copies.
298 extern char &RegisterCoalescerID;
300 /// MachineScheduler - This pass schedules machine instructions.
301 extern char &MachineSchedulerID;
303 /// SpillPlacement analysis. Suggest optimal placement of spill code between
305 extern char &SpillPlacementID;
307 /// UnreachableMachineBlockElimination - This pass removes unreachable
308 /// machine basic blocks.
309 extern char &UnreachableMachineBlockElimID;
311 /// DeadMachineInstructionElim - This pass removes dead machine instructions.
312 extern char &DeadMachineInstructionElimID;
314 /// FastRegisterAllocation Pass - This pass register allocates as fast as
315 /// possible. It is best suited for debug code where live ranges are short.
317 FunctionPass *createFastRegisterAllocator();
319 /// BasicRegisterAllocation Pass - This pass implements a degenerate global
320 /// register allocator using the basic regalloc framework.
322 FunctionPass *createBasicRegisterAllocator();
324 /// Greedy register allocation pass - This pass implements a global register
325 /// allocator for optimized builds.
327 FunctionPass *createGreedyRegisterAllocator();
329 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
330 /// Quadratic Prograaming (PBQP) based register allocator.
332 FunctionPass *createDefaultPBQPRegisterAllocator();
334 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
335 /// and eliminates abstract frame references.
336 extern char &PrologEpilogCodeInserterID;
338 /// ExpandPostRAPseudos - This pass expands pseudo instructions after
339 /// register allocation.
340 extern char &ExpandPostRAPseudosID;
342 /// createPostRAScheduler - This pass performs post register allocation
344 extern char &PostRASchedulerID;
346 /// BranchFolding - This pass performs machine code CFG based
347 /// optimizations to delete branches to branches, eliminate branches to
348 /// successor blocks (creating fall throughs), and eliminating branches over
350 extern char &BranchFolderPassID;
352 /// TailDuplicate - Duplicate blocks with unconditional branches
353 /// into tails of their predecessors.
354 extern char &TailDuplicateID;
356 /// IfConverter - This pass performs machine code if conversion.
357 extern char &IfConverterID;
359 /// MachineBlockPlacement - This pass places basic blocks based on branch
361 extern char &MachineBlockPlacementID;
363 /// MachineBlockPlacementStats - This pass collects statistics about the
364 /// basic block placement using branch probabilities and block frequency
366 extern char &MachineBlockPlacementStatsID;
368 /// Code Placement - This pass optimize code placement and aligns loop
369 /// headers to target specific alignment boundary.
370 extern char &CodePlacementOptID;
372 /// GCLowering Pass - Performs target-independent LLVM IR transformations for
373 /// highly portable strategies.
375 FunctionPass *createGCLoweringPass();
377 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points
378 /// in machine code. Must be added very late during code generation, just
379 /// prior to output, and importantly after all CFG transformations (such as
381 extern char &GCMachineCodeAnalysisID;
383 /// Deleter Pass - Releases GC metadata.
385 FunctionPass *createGCInfoDeleter();
387 /// Creates a pass to print GC metadata.
389 FunctionPass *createGCInfoPrinter(raw_ostream &OS);
391 /// MachineCSE - This pass performs global CSE on machine instructions.
392 extern char &MachineCSEID;
394 /// MachineLICM - This pass performs LICM on machine instructions.
395 extern char &MachineLICMID;
397 /// MachineSinking - This pass performs sinking on machine instructions.
398 extern char &MachineSinkingID;
400 /// MachineCopyPropagation - This pass performs copy propagation on
401 /// machine instructions.
402 extern char &MachineCopyPropagationID;
404 /// PeepholeOptimizer - This pass performs peephole optimizations -
405 /// like extension and comparison eliminations.
406 extern char &PeepholeOptimizerID;
408 /// OptimizePHIs - This pass optimizes machine instruction PHIs
409 /// to take advantage of opportunities created during DAG legalization.
410 extern char &OptimizePHIsID;
412 /// StackSlotColoring - This pass performs stack slot coloring.
413 extern char &StackSlotColoringID;
415 /// createStackProtectorPass - This pass adds stack protectors to functions.
417 FunctionPass *createStackProtectorPass(const TargetLowering *tli);
419 /// createMachineVerifierPass - This pass verifies cenerated machine code
420 /// instructions for correctness.
422 FunctionPass *createMachineVerifierPass(const char *Banner = 0);
424 /// createDwarfEHPass - This pass mulches exception handling code into a form
425 /// adapted to code generation. Required if using dwarf exception handling.
426 FunctionPass *createDwarfEHPass(const TargetMachine *tm);
428 /// createSjLjEHPass - This pass adapts exception handling code to use
429 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
431 FunctionPass *createSjLjEHPass(const TargetLowering *tli);
433 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack
434 /// slots relative to one another and allocates base registers to access them
435 /// when it is estimated by the target to be out of range of normal frame
436 /// pointer or stack pointer index addressing.
437 extern char &LocalStackSlotAllocationID;
439 /// ExpandISelPseudos - This pass expands pseudo-instructions.
440 extern char &ExpandISelPseudosID;
442 /// createExecutionDependencyFixPass - This pass fixes execution time
443 /// problems with dependent instructions, such as switching execution
444 /// domains to match.
446 /// The pass will examine instructions using and defining registers in RC.
448 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
450 /// UnpackMachineBundles - This pass unpack machine instruction bundles.
451 extern char &UnpackMachineBundlesID;
453 /// FinalizeMachineBundles - This pass finalize machine instruction
454 /// bundles (created earlier, e.g. during pre-RA scheduling).
455 extern char &FinalizeMachineBundlesID;
457 } // End llvm namespace