1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code generation
11 // passes provided by the LLVM backend.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_PASSES_H
16 #define LLVM_CODEGEN_PASSES_H
18 #include "llvm/Pass.h"
19 #include "llvm/Target/TargetMachine.h"
25 class MachineFunctionPass;
28 class ScheduleDAGInstrs;
30 class TargetLoweringBase;
31 class TargetRegisterClass;
33 struct MachineSchedContext;
35 // The old pass manager infrastructure is hidden in a legacy namespace now.
37 class PassManagerBase;
39 using legacy::PassManagerBase;
41 /// Discriminated union of Pass ID types.
43 /// The PassConfig API prefers dealing with IDs because they are safer and more
44 /// efficient. IDs decouple configuration from instantiation. This way, when a
45 /// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to
46 /// refer to a Pass pointer after adding it to a pass manager, which deletes
47 /// redundant pass instances.
49 /// However, it is convient to directly instantiate target passes with
50 /// non-default ctors. These often don't have a registered PassInfo. Rather than
51 /// force all target passes to implement the pass registry boilerplate, allow
52 /// the PassConfig API to handle either type.
54 /// AnalysisID is sadly char*, so PointerIntPair won't work.
55 class IdentifyingPassPtr {
62 IdentifyingPassPtr() : P(nullptr), IsInstance(false) {}
63 IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr), IsInstance(false) {}
64 IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {}
66 bool isValid() const { return P; }
67 bool isInstance() const { return IsInstance; }
69 AnalysisID getID() const {
70 assert(!IsInstance && "Not a Pass ID");
73 Pass *getInstance() const {
74 assert(IsInstance && "Not a Pass Instance");
79 template <> struct isPodLike<IdentifyingPassPtr> {
80 static const bool value = true;
83 /// Target-Independent Code Generator Pass Configuration Options.
85 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
86 /// to the internals of other CodeGen passes.
87 class TargetPassConfig : public ImmutablePass {
89 /// Pseudo Pass IDs. These are defined within TargetPassConfig because they
90 /// are unregistered pass IDs. They are only useful for use with
91 /// TargetPassConfig APIs to identify multiple occurrences of the same pass.
94 /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early
95 /// during codegen, on SSA form.
96 static char EarlyTailDuplicateID;
98 /// PostRAMachineLICM - A clone of the LICM pass that runs during late machine
99 /// optimization after regalloc.
100 static char PostRAMachineLICMID;
104 AnalysisID StartAfter;
105 AnalysisID StopAfter;
108 bool AddingMachinePasses;
112 PassConfigImpl *Impl; // Internal data structures
113 bool Initialized; // Flagged after all passes are configured.
115 // Target Pass Options
116 // Targets provide a default setting, user flags override.
120 /// Default setting for -enable-tail-merge on this target.
121 bool EnableTailMerge;
124 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
125 // Dummy constructor.
128 virtual ~TargetPassConfig();
132 /// Get the right type of TargetMachine for this target.
133 template<typename TMC> TMC &getTM() const {
134 return *static_cast<TMC*>(TM);
138 void setInitialized() { Initialized = true; }
140 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
142 /// setStartStopPasses - Set the StartAfter and StopAfter passes to allow
143 /// running only a portion of the normal code-gen pass sequence. If the
144 /// Start pass ID is zero, then compilation will begin at the normal point;
145 /// otherwise, clear the Started flag to indicate that passes should not be
146 /// added until the starting pass is seen. If the Stop pass ID is zero,
147 /// then compilation will continue to the end.
148 void setStartStopPasses(AnalysisID Start, AnalysisID Stop) {
151 Started = (StartAfter == nullptr);
154 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
156 bool getEnableTailMerge() const { return EnableTailMerge; }
157 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
159 /// Allow the target to override a specific pass without overriding the pass
160 /// pipeline. When passes are added to the standard pipeline at the
161 /// point where StandardID is expected, add TargetID in its place.
162 void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID);
164 /// Insert InsertedPassID pass after TargetPassID pass.
165 void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID);
167 /// Allow the target to enable a specific standard pass by default.
168 void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
170 /// Allow the target to disable a specific standard pass by default.
171 void disablePass(AnalysisID PassID) {
172 substitutePass(PassID, IdentifyingPassPtr());
175 /// Return the pass substituted for StandardID by the target.
176 /// If no substitution exists, return StandardID.
177 IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const;
179 /// Return true if the optimized regalloc pipeline is enabled.
180 bool getOptimizeRegAlloc() const;
182 /// Return true if the default global register allocator is in use and
183 /// has not be overriden on the command line with '-regalloc=...'
184 bool usingDefaultRegAlloc() const;
186 /// Add common target configurable passes that perform LLVM IR to IR
187 /// transforms following machine independent optimization.
188 virtual void addIRPasses();
190 /// Add passes to lower exception handling for the code generator.
191 void addPassesToHandleExceptions();
193 /// Add pass to prepare the LLVM IR for code generation. This should be done
194 /// before exception handling preparation passes.
195 virtual void addCodeGenPrepare();
197 /// Add common passes that perform LLVM IR to IR transforms in preparation for
198 /// instruction selection.
199 virtual void addISelPrepare();
201 /// addInstSelector - This method should install an instruction selector pass,
202 /// which converts from LLVM code to machine instructions.
203 virtual bool addInstSelector() {
207 /// Add the complete, standard set of LLVM CodeGen passes.
208 /// Fully developed targets will not generally override this.
209 virtual void addMachinePasses();
211 /// Create an instance of ScheduleDAGInstrs to be run within the standard
212 /// MachineScheduler pass for this function and target at the current
213 /// optimization level.
215 /// This can also be used to plug a new MachineSchedStrategy into an instance
216 /// of the standard ScheduleDAGMI:
217 /// return new ScheduleDAGMI(C, make_unique<MyStrategy>(C), /* IsPostRA= */false)
219 /// Return NULL to select the default (generic) machine scheduler.
220 virtual ScheduleDAGInstrs *
221 createMachineScheduler(MachineSchedContext *C) const {
225 /// Similar to createMachineScheduler but used when postRA machine scheduling
227 virtual ScheduleDAGInstrs *
228 createPostMachineScheduler(MachineSchedContext *C) const {
233 // Helper to verify the analysis is really immutable.
234 void setOpt(bool &Opt, bool Val);
236 /// Methods with trivial inline returns are convenient points in the common
237 /// codegen pass pipeline where targets may insert passes. Methods with
238 /// out-of-line standard implementations are major CodeGen stages called by
239 /// addMachinePasses. Some targets may override major stages when inserting
240 /// passes is insufficient, but maintaining overriden stages is more work.
243 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
244 /// passes (which are run just before instruction selector).
245 virtual bool addPreISel() {
249 /// addMachineSSAOptimization - Add standard passes that optimize machine
250 /// instructions in SSA form.
251 virtual void addMachineSSAOptimization();
253 /// Add passes that optimize instruction level parallelism for out-of-order
254 /// targets. These passes are run while the machine code is still in SSA
255 /// form, so they can use MachineTraceMetrics to control their heuristics.
257 /// All passes added here should preserve the MachineDominatorTree,
258 /// MachineLoopInfo, and MachineTraceMetrics analyses.
259 virtual bool addILPOpts() {
263 /// This method may be implemented by targets that want to run passes
264 /// immediately before register allocation.
265 virtual void addPreRegAlloc() { }
267 /// createTargetRegisterAllocator - Create the register allocator pass for
268 /// this target at the current optimization level.
269 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
271 /// addFastRegAlloc - Add the minimum set of target-independent passes that
272 /// are required for fast register allocation.
273 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
275 /// addOptimizedRegAlloc - Add passes related to register allocation.
276 /// LLVMTargetMachine provides standard regalloc passes for most targets.
277 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
279 /// addPreRewrite - Add passes to the optimized register allocation pipeline
280 /// after register allocation is complete, but before virtual registers are
281 /// rewritten to physical registers.
283 /// These passes must preserve VirtRegMap and LiveIntervals, and when running
284 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
285 /// When these passes run, VirtRegMap contains legal physreg assignments for
286 /// all virtual registers.
287 virtual bool addPreRewrite() {
291 /// This method may be implemented by targets that want to run passes after
292 /// register allocation pass pipeline but before prolog-epilog insertion.
293 virtual void addPostRegAlloc() { }
295 /// Add passes that optimize machine instructions after register allocation.
296 virtual void addMachineLateOptimization();
298 /// This method may be implemented by targets that want to run passes after
299 /// prolog-epilog insertion and before the second instruction scheduling pass.
300 virtual void addPreSched2() { }
302 /// addGCPasses - Add late codegen passes that analyze code for garbage
303 /// collection. This should return true if GC info should be printed after
305 virtual bool addGCPasses();
307 /// Add standard basic block placement passes.
308 virtual void addBlockPlacement();
310 /// This pass may be implemented by targets that want to run passes
311 /// immediately before machine code is emitted.
312 virtual void addPreEmitPass() { }
314 /// Utilities for targets to add passes to the pass manager.
317 /// Add a CodeGen pass at this point in the pipeline after checking overrides.
318 /// Return the pass that was added, or zero if no pass was added.
319 /// @p printAfter if true and adding a machine function pass add an extra
320 /// machine printer pass afterwards
321 /// @p verifyAfter if true and adding a machine function pass add an extra
322 /// machine verification pass afterwards.
323 AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true,
324 bool printAfter = true);
326 /// Add a pass to the PassManager if that pass is supposed to be run, as
327 /// determined by the StartAfter and StopAfter options. Takes ownership of the
329 /// @p printAfter if true and adding a machine function pass add an extra
330 /// machine printer pass afterwards
331 /// @p verifyAfter if true and adding a machine function pass add an extra
332 /// machine verification pass afterwards.
333 void addPass(Pass *P, bool verifyAfter = true, bool printAfter = true);
335 /// addMachinePasses helper to create the target-selected or overriden
337 FunctionPass *createRegAllocPass(bool Optimized);
339 /// printAndVerify - Add a pass to dump then verify the machine function, if
340 /// those steps are enabled.
342 void printAndVerify(const std::string &Banner);
344 /// Add a pass to print the machine function if printing is enabled.
345 void addPrintPass(const std::string &Banner);
347 /// Add a pass to perform basic verification of the machine function if
348 /// verification is enabled.
349 void addVerifyPass(const std::string &Banner);
353 /// List of target independent CodeGen pass IDs.
355 FunctionPass *createAtomicExpandPass(const TargetMachine *TM);
357 /// \brief Create a basic TargetTransformInfo analysis pass.
359 /// This pass implements the target transform info analysis using the target
360 /// independent information available to the LLVM code generator.
362 createBasicTargetTransformInfoPass(const TargetMachine *TM);
364 /// createUnreachableBlockEliminationPass - The LLVM code generator does not
365 /// work well with unreachable basic blocks (what live ranges make sense for a
366 /// block that cannot be reached?). As such, a code generator should either
367 /// not instruction select unreachable blocks, or run this pass as its
368 /// last LLVM modifying pass to clean up blocks that are not reachable from
370 FunctionPass *createUnreachableBlockEliminationPass();
372 /// MachineFunctionPrinter pass - This pass prints out the machine function to
373 /// the given stream as a debugging tool.
374 MachineFunctionPass *
375 createMachineFunctionPrinterPass(raw_ostream &OS,
376 const std::string &Banner ="");
378 /// createCodeGenPreparePass - Transform the code to expose more pattern
379 /// matching during instruction selection.
380 FunctionPass *createCodeGenPreparePass(const TargetMachine *TM = nullptr);
382 /// AtomicExpandID -- Lowers atomic operations in terms of either cmpxchg
383 /// load-linked/store-conditional loops.
384 extern char &AtomicExpandID;
386 /// MachineLoopInfo - This pass is a loop analysis pass.
387 extern char &MachineLoopInfoID;
389 /// MachineDominators - This pass is a machine dominators analysis pass.
390 extern char &MachineDominatorsID;
392 /// MachineDominanaceFrontier - This pass is a machine dominators analysis pass.
393 extern char &MachineDominanceFrontierID;
395 /// EdgeBundles analysis - Bundle machine CFG edges.
396 extern char &EdgeBundlesID;
398 /// LiveVariables pass - This pass computes the set of blocks in which each
399 /// variable is life and sets machine operand kill flags.
400 extern char &LiveVariablesID;
402 /// PHIElimination - This pass eliminates machine instruction PHI nodes
403 /// by inserting copy instructions. This destroys SSA information, but is the
404 /// desired input for some register allocators. This pass is "required" by
405 /// these register allocator like this: AU.addRequiredID(PHIEliminationID);
406 extern char &PHIEliminationID;
408 /// LiveIntervals - This analysis keeps track of the live ranges of virtual
409 /// and physical registers.
410 extern char &LiveIntervalsID;
412 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
413 extern char &LiveStacksID;
415 /// TwoAddressInstruction - This pass reduces two-address instructions to
416 /// use two operands. This destroys SSA information but it is desired by
417 /// register allocators.
418 extern char &TwoAddressInstructionPassID;
420 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
421 extern char &ProcessImplicitDefsID;
423 /// RegisterCoalescer - This pass merges live ranges to eliminate copies.
424 extern char &RegisterCoalescerID;
426 /// MachineScheduler - This pass schedules machine instructions.
427 extern char &MachineSchedulerID;
429 /// PostMachineScheduler - This pass schedules machine instructions postRA.
430 extern char &PostMachineSchedulerID;
432 /// SpillPlacement analysis. Suggest optimal placement of spill code between
434 extern char &SpillPlacementID;
436 /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as
437 /// assigned in VirtRegMap.
438 extern char &VirtRegRewriterID;
440 /// UnreachableMachineBlockElimination - This pass removes unreachable
441 /// machine basic blocks.
442 extern char &UnreachableMachineBlockElimID;
444 /// DeadMachineInstructionElim - This pass removes dead machine instructions.
445 extern char &DeadMachineInstructionElimID;
447 /// FastRegisterAllocation Pass - This pass register allocates as fast as
448 /// possible. It is best suited for debug code where live ranges are short.
450 FunctionPass *createFastRegisterAllocator();
452 /// BasicRegisterAllocation Pass - This pass implements a degenerate global
453 /// register allocator using the basic regalloc framework.
455 FunctionPass *createBasicRegisterAllocator();
457 /// Greedy register allocation pass - This pass implements a global register
458 /// allocator for optimized builds.
460 FunctionPass *createGreedyRegisterAllocator();
462 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
463 /// Quadratic Prograaming (PBQP) based register allocator.
465 FunctionPass *createDefaultPBQPRegisterAllocator();
467 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
468 /// and eliminates abstract frame references.
469 extern char &PrologEpilogCodeInserterID;
471 /// ExpandPostRAPseudos - This pass expands pseudo instructions after
472 /// register allocation.
473 extern char &ExpandPostRAPseudosID;
475 /// createPostRAScheduler - This pass performs post register allocation
477 extern char &PostRASchedulerID;
479 /// BranchFolding - This pass performs machine code CFG based
480 /// optimizations to delete branches to branches, eliminate branches to
481 /// successor blocks (creating fall throughs), and eliminating branches over
483 extern char &BranchFolderPassID;
485 /// MachineFunctionPrinterPass - This pass prints out MachineInstr's.
486 extern char &MachineFunctionPrinterPassID;
488 /// TailDuplicate - Duplicate blocks with unconditional branches
489 /// into tails of their predecessors.
490 extern char &TailDuplicateID;
492 /// MachineTraceMetrics - This pass computes critical path and CPU resource
493 /// usage in an ensemble of traces.
494 extern char &MachineTraceMetricsID;
496 /// EarlyIfConverter - This pass performs if-conversion on SSA form by
497 /// inserting cmov instructions.
498 extern char &EarlyIfConverterID;
500 /// This pass performs instruction combining using trace metrics to estimate
501 /// critical-path and resource depth.
502 extern char &MachineCombinerID;
504 /// StackSlotColoring - This pass performs stack coloring and merging.
505 /// It merges disjoint allocas to reduce the stack size.
506 extern char &StackColoringID;
508 /// IfConverter - This pass performs machine code if conversion.
509 extern char &IfConverterID;
511 /// MachineBlockPlacement - This pass places basic blocks based on branch
513 extern char &MachineBlockPlacementID;
515 /// MachineBlockPlacementStats - This pass collects statistics about the
516 /// basic block placement using branch probabilities and block frequency
518 extern char &MachineBlockPlacementStatsID;
520 /// GCLowering Pass - Performs target-independent LLVM IR transformations for
521 /// highly portable strategies.
523 FunctionPass *createGCLoweringPass();
525 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points
526 /// in machine code. Must be added very late during code generation, just
527 /// prior to output, and importantly after all CFG transformations (such as
529 extern char &GCMachineCodeAnalysisID;
531 /// Creates a pass to print GC metadata.
533 FunctionPass *createGCInfoPrinter(raw_ostream &OS);
535 /// MachineCSE - This pass performs global CSE on machine instructions.
536 extern char &MachineCSEID;
538 /// MachineLICM - This pass performs LICM on machine instructions.
539 extern char &MachineLICMID;
541 /// MachineSinking - This pass performs sinking on machine instructions.
542 extern char &MachineSinkingID;
544 /// MachineCopyPropagation - This pass performs copy propagation on
545 /// machine instructions.
546 extern char &MachineCopyPropagationID;
548 /// PeepholeOptimizer - This pass performs peephole optimizations -
549 /// like extension and comparison eliminations.
550 extern char &PeepholeOptimizerID;
552 /// OptimizePHIs - This pass optimizes machine instruction PHIs
553 /// to take advantage of opportunities created during DAG legalization.
554 extern char &OptimizePHIsID;
556 /// StackSlotColoring - This pass performs stack slot coloring.
557 extern char &StackSlotColoringID;
559 /// createStackProtectorPass - This pass adds stack protectors to functions.
561 FunctionPass *createStackProtectorPass(const TargetMachine *TM);
563 /// createMachineVerifierPass - This pass verifies cenerated machine code
564 /// instructions for correctness.
566 FunctionPass *createMachineVerifierPass(const std::string& Banner);
568 /// createDwarfEHPass - This pass mulches exception handling code into a form
569 /// adapted to code generation. Required if using dwarf exception handling.
570 FunctionPass *createDwarfEHPass(const TargetMachine *TM);
572 /// createSjLjEHPreparePass - This pass adapts exception handling code to use
573 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
575 FunctionPass *createSjLjEHPreparePass(const TargetMachine *TM);
577 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack
578 /// slots relative to one another and allocates base registers to access them
579 /// when it is estimated by the target to be out of range of normal frame
580 /// pointer or stack pointer index addressing.
581 extern char &LocalStackSlotAllocationID;
583 /// ExpandISelPseudos - This pass expands pseudo-instructions.
584 extern char &ExpandISelPseudosID;
586 /// createExecutionDependencyFixPass - This pass fixes execution time
587 /// problems with dependent instructions, such as switching execution
588 /// domains to match.
590 /// The pass will examine instructions using and defining registers in RC.
592 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
594 /// UnpackMachineBundles - This pass unpack machine instruction bundles.
595 extern char &UnpackMachineBundlesID;
597 /// FinalizeMachineBundles - This pass finalize machine instruction
598 /// bundles (created earlier, e.g. during pre-RA scheduling).
599 extern char &FinalizeMachineBundlesID;
601 /// StackMapLiveness - This pass analyses the register live-out set of
602 /// stackmap/patchpoint intrinsics and attaches the calculated information to
603 /// the intrinsic for later emission to the StackMap.
604 extern char &StackMapLivenessID;
606 /// createJumpInstrTables - This pass creates jump-instruction tables.
607 ModulePass *createJumpInstrTablesPass();
609 /// createForwardControlFlowIntegrityPass - This pass adds control-flow
611 ModulePass *createForwardControlFlowIntegrityPass();
612 } // End llvm namespace
614 /// This initializer registers TargetMachine constructor, so the pass being
615 /// initialized can use target dependent interfaces. Please do not move this
616 /// macro to be together with INITIALIZE_PASS, which is a complete target
617 /// independent initializer, and we don't want to make libScalarOpts depend
619 #define INITIALIZE_TM_PASS(passName, arg, name, cfg, analysis) \
620 static void* initialize##passName##PassOnce(PassRegistry &Registry) { \
621 PassInfo *PI = new PassInfo(name, arg, & passName ::ID, \
622 PassInfo::NormalCtor_t(callDefaultCtor< passName >), cfg, analysis, \
623 PassInfo::TargetMachineCtor_t(callTargetMachineCtor< passName >)); \
624 Registry.registerPass(*PI, true); \
627 void llvm::initialize##passName##Pass(PassRegistry &Registry) { \
628 CALL_ONCE_INITIALIZATION(initialize##passName##PassOnce) \