1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code generation
11 // passes provided by the LLVM backend.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_PASSES_H
16 #define LLVM_CODEGEN_PASSES_H
18 #include "llvm/Pass.h"
19 #include "llvm/Target/TargetMachine.h"
25 class MachineFunctionPass;
28 class TargetRegisterClass;
34 /// Target-Independent Code Generator Pass Configuration Options.
36 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
37 /// to the internals of other CodeGen passes.
38 class TargetPassConfig : public ImmutablePass {
42 bool Initialized; // Flagged after all passes are configured.
44 // Target Pass Options
45 // Targets provide a default setting, user flags override.
49 /// Default setting for -enable-tail-merge on this target.
53 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
57 virtual ~TargetPassConfig();
61 /// Get the right type of TargetMachine for this target.
62 template<typename TMC> TMC &getTM() const {
63 return *static_cast<TMC*>(TM);
66 const TargetLowering *getTargetLowering() const {
67 return TM->getTargetLowering();
70 void setInitialized() { Initialized = true; }
72 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
74 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
76 bool getEnableTailMerge() const { return EnableTailMerge; }
77 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
79 /// Add common target configurable passes that perform LLVM IR to IR
80 /// transforms following machine independent optimization.
81 virtual void addIRPasses();
83 /// Add common passes that perform LLVM IR to IR transforms in preparation for
84 /// instruction selection.
85 virtual void addISelPrepare();
87 /// addInstSelector - This method should install an instruction selector pass,
88 /// which converts from LLVM code to machine instructions.
89 virtual bool addInstSelector() {
93 /// Add the complete, standard set of LLVM CodeGen passes.
94 /// Fully developed targets will not generally override this.
95 virtual void addMachinePasses();
98 // Helper to verify the analysis is really immutable.
99 void setOpt(bool &Opt, bool Val);
101 /// Methods with trivial inline returns are convenient points in the common
102 /// codegen pass pipeline where targets may insert passes. Methods with
103 /// out-of-line standard implementations are major CodeGen stages called by
104 /// addMachinePasses. Some targets may override major stages when inserting
105 /// passes is insufficient, but maintaining overriden stages is more work.
108 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
109 /// passes (which are run just before instruction selector).
110 virtual bool addPreISel() {
114 /// addMachineSSAOptimization - Add standard passes that optimize machine
115 /// instructions in SSA form.
116 virtual void addMachineSSAOptimization();
118 /// addPreRegAlloc - This method may be implemented by targets that want to
119 /// run passes immediately before register allocation. This should return
120 /// true if -print-machineinstrs should print after these passes.
121 virtual bool addPreRegAlloc() {
125 // addRegAlloc - Add standard passes related to register allocation.
126 virtual void addRegAlloc();
128 /// addPostRegAlloc - This method may be implemented by targets that want
129 /// to run passes after register allocation but before prolog-epilog
130 /// insertion. This should return true if -print-machineinstrs should print
131 /// after these passes.
132 virtual bool addPostRegAlloc() {
136 /// Add passes that optimize machine instructions after register allocation.
137 virtual void addMachineLateOptimization();
139 /// addPreSched2 - This method may be implemented by targets that want to
140 /// run passes after prolog-epilog insertion and before the second instruction
141 /// scheduling pass. This should return true if -print-machineinstrs should
142 /// print after these passes.
143 virtual bool addPreSched2() {
147 /// Add standard basic block placement passes.
148 virtual void addBlockPlacement();
150 /// addPreEmitPass - This pass may be implemented by targets that want to run
151 /// passes immediately before machine code is emitted. This should return
152 /// true if -print-machineinstrs should print out the code after the passes.
153 virtual bool addPreEmitPass() {
157 /// Utilities for targets to add passes to the pass manager.
160 /// Add a target-independent CodeGen pass at this point in the pipeline.
161 void addPass(char &ID);
163 /// printNoVerify - Add a pass to dump the machine function, if debugging is
166 void printNoVerify(const char *Banner) const;
168 /// printAndVerify - Add a pass to dump then verify the machine function, if
169 /// those steps are enabled.
171 void printAndVerify(const char *Banner) const;
175 /// List of target independent CodeGen pass IDs.
177 /// createUnreachableBlockEliminationPass - The LLVM code generator does not
178 /// work well with unreachable basic blocks (what live ranges make sense for a
179 /// block that cannot be reached?). As such, a code generator should either
180 /// not instruction select unreachable blocks, or run this pass as its
181 /// last LLVM modifying pass to clean up blocks that are not reachable from
183 FunctionPass *createUnreachableBlockEliminationPass();
185 /// MachineFunctionPrinter pass - This pass prints out the machine function to
186 /// the given stream as a debugging tool.
187 MachineFunctionPass *
188 createMachineFunctionPrinterPass(raw_ostream &OS,
189 const std::string &Banner ="");
191 /// MachineLoopInfo - This pass is a loop analysis pass.
192 extern char &MachineLoopInfoID;
194 /// MachineLoopRanges - This pass is an on-demand loop coverage analysis.
195 extern char &MachineLoopRangesID;
197 /// MachineDominators - This pass is a machine dominators analysis pass.
198 extern char &MachineDominatorsID;
200 /// EdgeBundles analysis - Bundle machine CFG edges.
201 extern char &EdgeBundlesID;
203 /// PHIElimination - This pass eliminates machine instruction PHI nodes
204 /// by inserting copy instructions. This destroys SSA information, but is the
205 /// desired input for some register allocators. This pass is "required" by
206 /// these register allocator like this: AU.addRequiredID(PHIEliminationID);
207 extern char &PHIEliminationID;
209 /// StrongPHIElimination - This pass eliminates machine instruction PHI
210 /// nodes by inserting copy instructions. This destroys SSA information, but
211 /// is the desired input for some register allocators. This pass is
212 /// "required" by these register allocator like this:
213 /// AU.addRequiredID(PHIEliminationID);
214 /// This pass is still in development
215 extern char &StrongPHIEliminationID;
217 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
218 extern char &LiveStacksID;
220 /// TwoAddressInstruction - This pass reduces two-address instructions to
221 /// use two operands. This destroys SSA information but it is desired by
222 /// register allocators.
223 extern char &TwoAddressInstructionPassID;
225 /// RegisteCoalescer - This pass merges live ranges to eliminate copies.
226 extern char &RegisterCoalescerPassID;
228 /// MachineScheduler - This pass schedules machine instructions.
229 extern char &MachineSchedulerID;
231 /// SpillPlacement analysis. Suggest optimal placement of spill code between
233 extern char &SpillPlacementID;
235 /// UnreachableMachineBlockElimination - This pass removes unreachable
236 /// machine basic blocks.
237 extern char &UnreachableMachineBlockElimID;
239 /// DeadMachineInstructionElim - This pass removes dead machine instructions.
240 extern char &DeadMachineInstructionElimID;
242 /// Creates a register allocator as the user specified on the command line, or
243 /// picks one that matches OptLevel.
245 FunctionPass *createRegisterAllocator(CodeGenOpt::Level OptLevel);
247 /// FastRegisterAllocation Pass - This pass register allocates as fast as
248 /// possible. It is best suited for debug code where live ranges are short.
250 FunctionPass *createFastRegisterAllocator();
252 /// BasicRegisterAllocation Pass - This pass implements a degenerate global
253 /// register allocator using the basic regalloc framework.
255 FunctionPass *createBasicRegisterAllocator();
257 /// Greedy register allocation pass - This pass implements a global register
258 /// allocator for optimized builds.
260 FunctionPass *createGreedyRegisterAllocator();
262 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
263 /// Quadratic Prograaming (PBQP) based register allocator.
265 FunctionPass *createDefaultPBQPRegisterAllocator();
267 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
268 /// and eliminates abstract frame references.
269 extern char &PrologEpilogCodeInserterID;
271 /// ExpandPostRAPseudos - This pass expands pseudo instructions after
272 /// register allocation.
273 extern char &ExpandPostRAPseudosID;
275 /// createPostRAScheduler - This pass performs post register allocation
277 extern char &PostRASchedulerID;
279 /// BranchFolding - This pass performs machine code CFG based
280 /// optimizations to delete branches to branches, eliminate branches to
281 /// successor blocks (creating fall throughs), and eliminating branches over
283 extern char &BranchFolderPassID;
285 /// TailDuplicate - Duplicate blocks with unconditional branches
286 /// into tails of their predecessors.
287 extern char &TailDuplicateID;
289 /// IfConverter - This pass performs machine code if conversion.
290 extern char &IfConverterID;
292 /// MachineBlockPlacement - This pass places basic blocks based on branch
294 extern char &MachineBlockPlacementID;
296 /// MachineBlockPlacementStats - This pass collects statistics about the
297 /// basic block placement using branch probabilities and block frequency
299 extern char &MachineBlockPlacementStatsID;
301 /// Code Placement - This pass optimize code placement and aligns loop
302 /// headers to target specific alignment boundary.
303 extern char &CodePlacementOptID;
305 /// GCLowering Pass - Performs target-independent LLVM IR transformations for
306 /// highly portable strategies.
308 FunctionPass *createGCLoweringPass();
310 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points
311 /// in machine code. Must be added very late during code generation, just
312 /// prior to output, and importantly after all CFG transformations (such as
314 extern char &GCMachineCodeAnalysisID;
316 /// Deleter Pass - Releases GC metadata.
318 FunctionPass *createGCInfoDeleter();
320 /// Creates a pass to print GC metadata.
322 FunctionPass *createGCInfoPrinter(raw_ostream &OS);
324 /// MachineCSE - This pass performs global CSE on machine instructions.
325 extern char &MachineCSEID;
327 /// MachineLICM - This pass performs LICM on machine instructions.
328 extern char &MachineLICMID;
330 /// MachineSinking - This pass performs sinking on machine instructions.
331 extern char &MachineSinkingID;
333 /// MachineCopyPropagation - This pass performs copy propagation on
334 /// machine instructions.
335 extern char &MachineCopyPropagationID;
337 /// PeepholeOptimizer - This pass performs peephole optimizations -
338 /// like extension and comparison eliminations.
339 extern char &PeepholeOptimizerID;
341 /// OptimizePHIs - This pass optimizes machine instruction PHIs
342 /// to take advantage of opportunities created during DAG legalization.
343 extern char &OptimizePHIsID;
345 /// StackSlotColoring - This pass performs stack slot coloring.
346 extern char &StackSlotColoringID;
348 /// createStackProtectorPass - This pass adds stack protectors to functions.
350 FunctionPass *createStackProtectorPass(const TargetLowering *tli);
352 /// createMachineVerifierPass - This pass verifies cenerated machine code
353 /// instructions for correctness.
355 FunctionPass *createMachineVerifierPass(const char *Banner = 0);
357 /// createDwarfEHPass - This pass mulches exception handling code into a form
358 /// adapted to code generation. Required if using dwarf exception handling.
359 FunctionPass *createDwarfEHPass(const TargetMachine *tm);
361 /// createSjLjEHPass - This pass adapts exception handling code to use
362 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
364 FunctionPass *createSjLjEHPass(const TargetLowering *tli);
366 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack
367 /// slots relative to one another and allocates base registers to access them
368 /// when it is estimated by the target to be out of range of normal frame
369 /// pointer or stack pointer index addressing.
370 extern char &LocalStackSlotAllocationID;
372 /// ExpandISelPseudos - This pass expands pseudo-instructions.
373 extern char &ExpandISelPseudosID;
375 /// createExecutionDependencyFixPass - This pass fixes execution time
376 /// problems with dependent instructions, such as switching execution
377 /// domains to match.
379 /// The pass will examine instructions using and defining registers in RC.
381 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
383 /// UnpackMachineBundles - This pass unpack machine instruction bundles.
384 extern char &UnpackMachineBundlesID;
386 /// FinalizeMachineBundles - This pass finalize machine instruction
387 /// bundles (created earlier, e.g. during pre-RA scheduling).
388 extern char &FinalizeMachineBundlesID;
390 } // End llvm namespace