1 //===-- RegisterClassInfo.h - Dynamic Register Class Info -*- C++ -*-------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the RegisterClassInfo class which provides dynamic
11 // information about target register classes. Callee saved and reserved
12 // registers depends on calling conventions and other dynamic information, so
13 // some things cannot be determined statically.
15 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_CODEGEN_REGISTERCLASSINFO_H
18 #define LLVM_CODEGEN_REGISTERCLASSINFO_H
20 #include "llvm/ADT/ArrayRef.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/OwningPtr.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
27 class RegisterClassInfo {
33 uint16_t LastCostChange;
34 OwningArrayPtr<MCPhysReg> Order;
37 : Tag(0), NumRegs(0), ProperSubClass(false), MinCost(0),
40 operator ArrayRef<MCPhysReg>() const {
41 return makeArrayRef(Order.get(), NumRegs);
45 // Brief cached information for each register class.
46 OwningArrayPtr<RCInfo> RegClass;
48 // Tag changes whenever cached information needs to be recomputed. An RCInfo
49 // entry is valid when its tag matches.
52 const MachineFunction *MF;
53 const TargetRegisterInfo *TRI;
55 // Callee saved registers of last MF. Assumed to be valid until the next
56 // runOnFunction() call.
57 const uint16_t *CalleeSaved;
59 // Map register number to CalleeSaved index + 1;
60 SmallVector<uint8_t, 4> CSRNum;
62 // Reserved registers in the current MF.
65 // Compute all information about RC.
66 void compute(const TargetRegisterClass *RC) const;
68 // Return an up-to-date RCInfo for RC.
69 const RCInfo &get(const TargetRegisterClass *RC) const {
70 const RCInfo &RCI = RegClass[RC->getID()];
79 /// runOnFunction - Prepare to answer questions about MF. This must be called
80 /// before any other methods are used.
81 void runOnMachineFunction(const MachineFunction &MF);
83 /// getNumAllocatableRegs - Returns the number of actually allocatable
84 /// registers in RC in the current function.
85 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
86 return get(RC).NumRegs;
89 /// getOrder - Returns the preferred allocation order for RC. The order
90 /// contains no reserved registers, and registers that alias callee saved
91 /// registers come last.
92 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const {
96 /// isProperSubClass - Returns true if RC has a legal super-class with more
97 /// allocatable registers.
99 /// Register classes like GR32_NOSP are not proper sub-classes because %esp
100 /// is not allocatable. Similarly, tGPR is not a proper sub-class in Thumb
101 /// mode because the GPR super-class is not legal.
102 bool isProperSubClass(const TargetRegisterClass *RC) const {
103 return get(RC).ProperSubClass;
106 /// getLastCalleeSavedAlias - Returns the last callee saved register that
107 /// overlaps PhysReg, or 0 if Reg doesn't overlap a CSR.
108 unsigned getLastCalleeSavedAlias(unsigned PhysReg) const {
109 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
110 if (unsigned N = CSRNum[PhysReg])
111 return CalleeSaved[N-1];
115 /// Get the minimum register cost in RC's allocation order.
116 /// This is the smallest value returned by TRI->getCostPerUse(Reg) for all
117 /// the registers in getOrder(RC).
118 unsigned getMinCost(const TargetRegisterClass *RC) {
119 return get(RC).MinCost;
122 /// Get the position of the last cost change in getOrder(RC).
124 /// All registers in getOrder(RC).slice(getLastCostChange(RC)) will have the
125 /// same cost according to TRI->getCostPerUse().
126 unsigned getLastCostChange(const TargetRegisterClass *RC) {
127 return get(RC).LastCostChange;
130 } // end namespace llvm