1 //===-- RegisterScavenging.h - Machine register scavenging ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the machine register scavenger class. It can provide
11 // information such as unused register at any point in a machine basic block.
12 // It also provides a mechanism to make registers availbale by evicting them
15 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_CODEGEN_REGISTER_SCAVENGING_H
18 #define LLVM_CODEGEN_REGISTER_SCAVENGING_H
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/ADT/BitVector.h"
25 class MachineRegisterInfo;
26 class TargetRegisterInfo;
27 class TargetInstrInfo;
28 class TargetRegisterClass;
31 MachineBasicBlock *MBB;
32 MachineBasicBlock::iterator MBBI;
35 /// Tracking - True if RegScavenger is currently tracking the liveness of
39 /// ScavengingFrameIndex - Special spill slot used for scavenging a register
40 /// post register allocation.
41 int ScavengingFrameIndex;
43 /// ScavengedReg - If none zero, the specific register is currently being
44 /// scavenged. That is, it is spilled to the special scavenging stack slot.
45 unsigned ScavengedReg;
47 /// ScavengedRC - Register class of the scavenged register.
49 const TargetRegisterClass *ScavengedRC;
51 /// RegsAvailable - The current state of all the physical registers immediately
52 /// before MBBI. One bit per physical register. If bit is set that means it's
53 /// available, unset means the register is currently being used.
54 BitVector RegsAvailable;
56 /// ImplicitDefed - If bit is set that means the register is defined by an
57 /// implicit_def instructions. That means it can be clobbered at will.
58 BitVector ImplicitDefed;
62 : MBB(NULL), NumPhysRegs(0), Tracking(false),
63 ScavengingFrameIndex(-1), ScavengedReg(0), ScavengedRC(NULL) {}
65 explicit RegScavenger(MachineBasicBlock *mbb)
66 : MBB(mbb), NumPhysRegs(0), Tracking(false),
67 ScavengingFrameIndex(-1), ScavengedReg(0), ScavengedRC(NULL) {}
69 /// enterBasicBlock - Start tracking liveness from the begin of the specific
71 void enterBasicBlock(MachineBasicBlock *mbb);
73 /// forward / backward - Move the internal MBB iterator and update register
78 /// forward / backward - Move the internal MBB iterator and update register
79 /// states until it has processed the specific iterator.
80 void forward(MachineBasicBlock::iterator I) {
81 while (MBBI != I) forward();
83 void backward(MachineBasicBlock::iterator I) {
84 while (MBBI != I) backward();
87 /// skipTo - Move the internal MBB iterator but do not update register states.
89 void skipTo(MachineBasicBlock::iterator I) { MBBI = I; }
91 /// isReserved - Returns true if a register is reserved. It is never "unused".
92 bool isReserved(unsigned Reg) const { return ReservedRegs[Reg]; }
94 /// isUsed / isUsed - Test if a register is currently being used.
96 bool isUsed(unsigned Reg) const { return !RegsAvailable[Reg]; }
97 bool isUnused(unsigned Reg) const { return RegsAvailable[Reg]; }
99 bool isImplicitlyDefined(unsigned Reg) const { return ImplicitDefed[Reg]; }
101 /// getRegsUsed - return all registers currently in use in used.
102 void getRegsUsed(BitVector &used, bool includeReserved);
104 /// setUsed / setUnused - Mark the state of one or a number of registers.
106 void setUsed(unsigned Reg, bool ImpDef = false);
107 void setUsed(BitVector Regs, bool ImpDef = false) {
108 RegsAvailable &= ~Regs;
110 ImplicitDefed |= Regs;
112 ImplicitDefed &= ~Regs;
114 void setUnused(unsigned Reg, const MachineInstr *MI);
115 void setUnused(BitVector Regs) {
116 RegsAvailable |= Regs;
117 ImplicitDefed &= ~Regs;
120 /// FindUnusedReg - Find a unused register of the specified register class
121 /// from the specified set of registers. It return 0 is none is found.
122 unsigned FindUnusedReg(const TargetRegisterClass *RegClass,
123 const BitVector &Candidates) const;
125 /// FindUnusedReg - Find a unused register of the specified register class.
126 /// Exclude callee saved registers if directed. It return 0 is none is found.
127 unsigned FindUnusedReg(const TargetRegisterClass *RegClass,
128 bool ExCalleeSaved = false) const;
130 /// setScavengingFrameIndex / getScavengingFrameIndex - accessor and setter of
131 /// ScavengingFrameIndex.
132 void setScavengingFrameIndex(int FI) { ScavengingFrameIndex = FI; }
133 int getScavengingFrameIndex() const { return ScavengingFrameIndex; }
135 /// scavengeRegister - Make a register of the specific register class
136 /// available and do the appropriate bookkeeping. SPAdj is the stack
137 /// adjustment due to call frame, it's passed along to eliminateFrameIndex().
138 /// Returns the scavenged register.
139 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
140 MachineBasicBlock::iterator I, int SPAdj);
141 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {
142 return scavengeRegister(RegClass, MBBI, SPAdj);
146 const TargetRegisterInfo *TRI;
147 const TargetInstrInfo *TII;
148 MachineRegisterInfo* MRI;
150 /// CalleeSavedrRegs - A bitvector of callee saved registers for the target.
152 BitVector CalleeSavedRegs;
154 /// ReservedRegs - A bitvector of reserved registers.
156 BitVector ReservedRegs;
158 /// restoreScavengedReg - Restore scavenged by loading it back from the
159 /// emergency spill slot. Mark it used.
160 void restoreScavengedReg();
163 } // End llvm namespace