1 //===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAG class, which is used as the common
11 // base class for instruction schedulers.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SCHEDULEDAG_H
16 #define LLVM_CODEGEN_SCHEDULEDAG_H
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/GraphTraits.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/PointerIntPair.h"
29 class MachineConstantPool;
30 class MachineFunction;
31 class MachineRegisterInfo;
33 class TargetRegisterInfo;
36 class TargetInstrInfo;
37 class TargetInstrDesc;
39 class TargetRegisterClass;
40 template<class Graph> class GraphWriter;
42 /// SDep - Scheduling dependency. This represents one direction of an
43 /// edge in the scheduling DAG.
46 /// Kind - These are the different kinds of scheduling dependencies.
48 Data, ///< Regular data dependence (aka true-dependence).
49 Anti, ///< A register anti-dependedence (aka WAR).
50 Output, ///< A register output-dependence (aka WAW).
51 Order ///< Any other ordering dependency.
55 /// Dep - A pointer to the depending/depended-on SUnit, and an enum
56 /// indicating the kind of the dependency.
57 PointerIntPair<SUnit *, 2, Kind> Dep;
59 /// Contents - A union discriminated by the dependence kind.
61 /// Reg - For Data, Anti, and Output dependencies, the associated
62 /// register. For Data dependencies that don't currently have a register
63 /// assigned, this is set to zero.
66 /// Order - Additional information about Order dependencies.
68 /// isNormalMemory - True if both sides of the dependence
69 /// access memory in non-volatile and fully modeled ways.
70 bool isNormalMemory : 1;
72 /// isMustAlias - True if both sides of the dependence are known to
73 /// access the same memory.
76 /// isArtificial - True if this is an artificial dependency, meaning
77 /// it is not necessary for program correctness, and may be safely
78 /// deleted if necessary.
79 bool isArtificial : 1;
83 /// Latency - The time associated with this edge. Often this is just
84 /// the value of the Latency field of the predecessor, however advanced
85 /// models may provide additional information about specific edges.
89 /// SDep - Construct a null SDep. This is only for use by container
90 /// classes which require default constructors. SUnits may not
91 /// have null SDep edges.
92 SDep() : Dep(0, Data) {}
94 /// SDep - Construct an SDep with the specified values.
95 SDep(SUnit *S, Kind kind, unsigned latency = 1, unsigned Reg = 0,
96 bool isNormalMemory = false, bool isMustAlias = false,
97 bool isArtificial = false)
98 : Dep(S, kind), Contents(), Latency(latency) {
103 "SDep::Anti and SDep::Output must use a non-zero Reg!");
106 assert(!isMustAlias && "isMustAlias only applies with SDep::Order!");
107 assert(!isArtificial && "isArtificial only applies with SDep::Order!");
111 assert(Reg == 0 && "Reg given for non-register dependence!");
112 Contents.Order.isNormalMemory = isNormalMemory;
113 Contents.Order.isMustAlias = isMustAlias;
114 Contents.Order.isArtificial = isArtificial;
119 bool operator==(const SDep &Other) const {
120 if (Dep != Other.Dep || Latency != Other.Latency) return false;
121 switch (Dep.getInt()) {
125 return Contents.Reg == Other.Contents.Reg;
127 return Contents.Order.isNormalMemory ==
128 Other.Contents.Order.isNormalMemory &&
129 Contents.Order.isMustAlias == Other.Contents.Order.isMustAlias &&
130 Contents.Order.isArtificial == Other.Contents.Order.isArtificial;
132 assert(0 && "Invalid dependency kind!");
136 bool operator!=(const SDep &Other) const {
137 return !operator==(Other);
140 /// getLatency - Return the latency value for this edge, which roughly
141 /// means the minimum number of cycles that must elapse between the
142 /// predecessor and the successor, given that they have this edge
144 unsigned getLatency() const {
148 /// setLatency - Set the latency for this edge.
149 void setLatency(unsigned Lat) {
153 //// getSUnit - Return the SUnit to which this edge points.
154 SUnit *getSUnit() const {
155 return Dep.getPointer();
158 //// setSUnit - Assign the SUnit to which this edge points.
159 void setSUnit(SUnit *SU) {
163 /// getKind - Return an enum value representing the kind of the dependence.
164 Kind getKind() const {
168 /// isCtrl - Shorthand for getKind() != SDep::Data.
169 bool isCtrl() const {
170 return getKind() != Data;
173 /// isNormalMemory - Test if this is an Order dependence between two
174 /// memory accesses where both sides of the dependence access memory
175 /// in non-volatile and fully modeled ways.
176 bool isNormalMemory() const {
177 return getKind() == Order && Contents.Order.isNormalMemory;
180 /// isMustAlias - Test if this is an Order dependence that is marked
181 /// as "must alias", meaning that the SUnits at either end of the edge
182 /// have a memory dependence on a known memory location.
183 bool isMustAlias() const {
184 return getKind() == Order && Contents.Order.isMustAlias;
187 /// isArtificial - Test if this is an Order dependence that is marked
188 /// as "artificial", meaning it isn't necessary for correctness.
189 bool isArtificial() const {
190 return getKind() == Order && Contents.Order.isArtificial;
193 /// isAssignedRegDep - Test if this is a Data dependence that is
194 /// associated with a register.
195 bool isAssignedRegDep() const {
196 return getKind() == Data && Contents.Reg != 0;
199 /// getReg - Return the register associated with this edge. This is
200 /// only valid on Data, Anti, and Output edges. On Data edges, this
201 /// value may be zero, meaning there is no associated register.
202 unsigned getReg() const {
203 assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
204 "getReg called on non-register dependence edge!");
208 /// setReg - Assign the associated register for this edge. This is
209 /// only valid on Data, Anti, and Output edges. On Anti and Output
210 /// edges, this value must not be zero. On Data edges, the value may
211 /// be zero, which would mean that no specific register is associated
213 void setReg(unsigned Reg) {
214 assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
215 "setReg called on non-register dependence edge!");
216 assert((getKind() != Anti || Reg != 0) &&
217 "SDep::Anti edge cannot use the zero register!");
218 assert((getKind() != Output || Reg != 0) &&
219 "SDep::Output edge cannot use the zero register!");
225 struct isPodLike<SDep> { static const bool value = true; };
227 /// SUnit - Scheduling unit. This is a node in the scheduling DAG.
230 SDNode *Node; // Representative node.
231 MachineInstr *Instr; // Alternatively, a MachineInstr.
233 SUnit *OrigNode; // If not this, the node from which
234 // this node was cloned.
236 // Preds/Succs - The SUnits before/after us in the graph.
237 SmallVector<SDep, 4> Preds; // All sunit predecessors.
238 SmallVector<SDep, 4> Succs; // All sunit successors.
240 typedef SmallVector<SDep, 4>::iterator pred_iterator;
241 typedef SmallVector<SDep, 4>::iterator succ_iterator;
242 typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator;
243 typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator;
245 unsigned NodeNum; // Entry # of node in the node vector.
246 unsigned NodeQueueId; // Queue id of node.
247 unsigned NumPreds; // # of SDep::Data preds.
248 unsigned NumSuccs; // # of SDep::Data sucss.
249 unsigned NumPredsLeft; // # of preds not scheduled.
250 unsigned NumSuccsLeft; // # of succs not scheduled.
251 unsigned short NumRegDefsLeft; // # of reg defs with no scheduled use.
252 unsigned short Latency; // Node latency.
253 bool isVRegCycle : 1; // May use and def the same vreg.
254 bool isCall : 1; // Is a function call.
255 bool isCallOp : 1; // Is a function call operand.
256 bool isTwoAddress : 1; // Is a two-address instruction.
257 bool isCommutable : 1; // Is a commutable instruction.
258 bool hasPhysRegDefs : 1; // Has physreg defs that are being used.
259 bool hasPhysRegClobbers : 1; // Has any physreg defs, used or not.
260 bool isPending : 1; // True once pending.
261 bool isAvailable : 1; // True once available.
262 bool isScheduled : 1; // True once scheduled.
263 bool isScheduleHigh : 1; // True if preferable to schedule high.
264 bool isScheduleLow : 1; // True if preferable to schedule low.
265 bool isCloned : 1; // True if this node has been cloned.
266 Sched::Preference SchedulingPref; // Scheduling preference.
269 bool isDepthCurrent : 1; // True if Depth is current.
270 bool isHeightCurrent : 1; // True if Height is current.
271 unsigned Depth; // Node depth.
272 unsigned Height; // Node height.
274 const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null.
275 const TargetRegisterClass *CopySrcRC;
277 /// SUnit - Construct an SUnit for pre-regalloc scheduling to represent
278 /// an SDNode and any nodes flagged to it.
279 SUnit(SDNode *node, unsigned nodenum)
280 : Node(node), Instr(0), OrigNode(0), NodeNum(nodenum),
281 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
282 NumSuccsLeft(0), NumRegDefsLeft(0), Latency(0),
283 isVRegCycle(false), isCall(false), isCallOp(false), isTwoAddress(false),
284 isCommutable(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
285 isPending(false), isAvailable(false), isScheduled(false),
286 isScheduleHigh(false), isScheduleLow(false), isCloned(false),
287 SchedulingPref(Sched::None),
288 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
289 CopyDstRC(NULL), CopySrcRC(NULL) {}
291 /// SUnit - Construct an SUnit for post-regalloc scheduling to represent
293 SUnit(MachineInstr *instr, unsigned nodenum)
294 : Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum),
295 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
296 NumSuccsLeft(0), NumRegDefsLeft(0), Latency(0),
297 isVRegCycle(false), isCall(false), isCallOp(false), isTwoAddress(false),
298 isCommutable(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
299 isPending(false), isAvailable(false), isScheduled(false),
300 isScheduleHigh(false), isScheduleLow(false), isCloned(false),
301 SchedulingPref(Sched::None),
302 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
303 CopyDstRC(NULL), CopySrcRC(NULL) {}
305 /// SUnit - Construct a placeholder SUnit.
307 : Node(0), Instr(0), OrigNode(0), NodeNum(~0u),
308 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
309 NumSuccsLeft(0), NumRegDefsLeft(0), Latency(0),
310 isVRegCycle(false), isCall(false), isCallOp(false), isTwoAddress(false),
311 isCommutable(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
312 isPending(false), isAvailable(false), isScheduled(false),
313 isScheduleHigh(false), isScheduleLow(false), isCloned(false),
314 SchedulingPref(Sched::None),
315 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
316 CopyDstRC(NULL), CopySrcRC(NULL) {}
318 /// setNode - Assign the representative SDNode for this SUnit.
319 /// This may be used during pre-regalloc scheduling.
320 void setNode(SDNode *N) {
321 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!");
325 /// getNode - Return the representative SDNode for this SUnit.
326 /// This may be used during pre-regalloc scheduling.
327 SDNode *getNode() const {
328 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!");
332 /// isInstr - Return true if this SUnit refers to a machine instruction as
333 /// opposed to an SDNode.
334 bool isInstr() const { return Instr; }
336 /// setInstr - Assign the instruction for the SUnit.
337 /// This may be used during post-regalloc scheduling.
338 void setInstr(MachineInstr *MI) {
339 assert(!Node && "Setting MachineInstr of SUnit with SDNode!");
343 /// getInstr - Return the representative MachineInstr for this SUnit.
344 /// This may be used during post-regalloc scheduling.
345 MachineInstr *getInstr() const {
346 assert(!Node && "Reading MachineInstr of SUnit with SDNode!");
350 /// addPred - This adds the specified edge as a pred of the current node if
351 /// not already. It also adds the current node as a successor of the
353 bool addPred(const SDep &D);
355 /// removePred - This removes the specified edge as a pred of the current
356 /// node if it exists. It also removes the current node as a successor of
357 /// the specified node.
358 void removePred(const SDep &D);
360 /// getDepth - Return the depth of this node, which is the length of the
361 /// maximum path up to any node which has no predecessors.
362 unsigned getDepth() const {
364 const_cast<SUnit *>(this)->ComputeDepth();
368 /// getHeight - Return the height of this node, which is the length of the
369 /// maximum path down to any node which has no successors.
370 unsigned getHeight() const {
371 if (!isHeightCurrent)
372 const_cast<SUnit *>(this)->ComputeHeight();
376 /// setDepthToAtLeast - If NewDepth is greater than this node's
377 /// depth value, set it to be the new depth value. This also
378 /// recursively marks successor nodes dirty.
379 void setDepthToAtLeast(unsigned NewDepth);
381 /// setDepthToAtLeast - If NewDepth is greater than this node's
382 /// depth value, set it to be the new height value. This also
383 /// recursively marks predecessor nodes dirty.
384 void setHeightToAtLeast(unsigned NewHeight);
386 /// setDepthDirty - Set a flag in this node to indicate that its
387 /// stored Depth value will require recomputation the next time
388 /// getDepth() is called.
389 void setDepthDirty();
391 /// setHeightDirty - Set a flag in this node to indicate that its
392 /// stored Height value will require recomputation the next time
393 /// getHeight() is called.
394 void setHeightDirty();
396 /// isPred - Test if node N is a predecessor of this node.
397 bool isPred(SUnit *N) {
398 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
399 if (Preds[i].getSUnit() == N)
404 /// isSucc - Test if node N is a successor of this node.
405 bool isSucc(SUnit *N) {
406 for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i)
407 if (Succs[i].getSUnit() == N)
412 void dump(const ScheduleDAG *G) const;
413 void dumpAll(const ScheduleDAG *G) const;
414 void print(raw_ostream &O, const ScheduleDAG *G) const;
418 void ComputeHeight();
421 //===--------------------------------------------------------------------===//
422 /// SchedulingPriorityQueue - This interface is used to plug different
423 /// priorities computation algorithms into the list scheduler. It implements
424 /// the interface of a standard priority queue, where nodes are inserted in
425 /// arbitrary order and returned in priority order. The computation of the
426 /// priority and the representation of the queue are totally up to the
427 /// implementation to decide.
429 class SchedulingPriorityQueue {
433 SchedulingPriorityQueue(bool rf = false):
434 CurCycle(0), HasReadyFilter(rf) {}
435 virtual ~SchedulingPriorityQueue() {}
437 virtual bool isBottomUp() const = 0;
439 virtual void initNodes(std::vector<SUnit> &SUnits) = 0;
440 virtual void addNode(const SUnit *SU) = 0;
441 virtual void updateNode(const SUnit *SU) = 0;
442 virtual void releaseState() = 0;
444 virtual bool empty() const = 0;
446 bool hasReadyFilter() const { return HasReadyFilter; }
448 virtual bool tracksRegPressure() const { return false; }
450 virtual bool isReady(SUnit *) const {
451 assert(!HasReadyFilter && "The ready filter must override isReady()");
454 virtual void push(SUnit *U) = 0;
456 void push_all(const std::vector<SUnit *> &Nodes) {
457 for (std::vector<SUnit *>::const_iterator I = Nodes.begin(),
458 E = Nodes.end(); I != E; ++I)
462 virtual SUnit *pop() = 0;
464 virtual void remove(SUnit *SU) = 0;
466 virtual void dump(ScheduleDAG *) const {}
468 /// ScheduledNode - As each node is scheduled, this method is invoked. This
469 /// allows the priority function to adjust the priority of related
470 /// unscheduled nodes, for example.
472 virtual void ScheduledNode(SUnit *) {}
474 virtual void UnscheduledNode(SUnit *) {}
476 void setCurCycle(unsigned Cycle) {
480 unsigned getCurCycle() const {
487 MachineBasicBlock *BB; // The block in which to insert instructions
488 MachineBasicBlock::iterator InsertPos;// The position to insert instructions
489 const TargetMachine &TM; // Target processor
490 const TargetInstrInfo *TII; // Target instruction information
491 const TargetRegisterInfo *TRI; // Target processor register info
492 MachineFunction &MF; // Machine function
493 MachineRegisterInfo &MRI; // Virtual/real register map
494 std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s
495 // represent noop instructions.
496 std::vector<SUnit> SUnits; // The scheduling units.
497 SUnit EntrySU; // Special node for the region entry.
498 SUnit ExitSU; // Special node for the region exit.
501 static const bool StressSched = false;
506 explicit ScheduleDAG(MachineFunction &mf);
508 virtual ~ScheduleDAG();
510 /// getInstrDesc - Return the TargetInstrDesc of this SUnit.
511 /// Return NULL for SDNodes without a machine opcode.
512 const TargetInstrDesc *getInstrDesc(const SUnit *SU) const {
513 if (SU->isInstr()) return &SU->getInstr()->getDesc();
514 return getNodeDesc(SU->getNode());
517 /// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered
522 /// EmitSchedule - Insert MachineInstrs into the MachineBasicBlock
523 /// according to the order specified in Sequence.
525 virtual MachineBasicBlock *EmitSchedule() = 0;
527 void dumpSchedule() const;
529 virtual void dumpNode(const SUnit *SU) const = 0;
531 /// getGraphNodeLabel - Return a label for an SUnit node in a visualization
532 /// of the ScheduleDAG.
533 virtual std::string getGraphNodeLabel(const SUnit *SU) const = 0;
535 /// addCustomGraphFeatures - Add custom features for a visualization of
537 virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {}
540 /// VerifySchedule - Verify that all SUnits were scheduled and that
541 /// their state is consistent.
542 void VerifySchedule(bool isBottomUp);
546 /// Run - perform scheduling.
548 void Run(MachineBasicBlock *bb, MachineBasicBlock::iterator insertPos);
550 /// BuildSchedGraph - Build SUnits and set up their Preds and Succs
551 /// to form the scheduling dependency graph.
553 virtual void BuildSchedGraph(AliasAnalysis *AA) = 0;
555 /// ComputeLatency - Compute node latency.
557 virtual void ComputeLatency(SUnit *SU) = 0;
559 /// ComputeOperandLatency - Override dependence edge latency using
560 /// operand use/def information
562 virtual void ComputeOperandLatency(SUnit *, SUnit *,
565 /// Schedule - Order nodes according to selected style, filling
566 /// in the Sequence member.
568 virtual void Schedule() = 0;
570 /// ForceUnitLatencies - Return true if all scheduling edges should be given
571 /// a latency value of one. The default is to return false; schedulers may
572 /// override this as needed.
573 virtual bool ForceUnitLatencies() const { return false; }
575 /// EmitNoop - Emit a noop instruction.
579 void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap);
582 // Return the TargetInstrDesc of this SDNode or NULL.
583 const TargetInstrDesc *getNodeDesc(const SDNode *Node) const;
586 class SUnitIterator : public std::iterator<std::forward_iterator_tag,
591 SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {}
593 bool operator==(const SUnitIterator& x) const {
594 return Operand == x.Operand;
596 bool operator!=(const SUnitIterator& x) const { return !operator==(x); }
598 const SUnitIterator &operator=(const SUnitIterator &I) {
599 assert(I.Node==Node && "Cannot assign iterators to two different nodes!");
604 pointer operator*() const {
605 return Node->Preds[Operand].getSUnit();
607 pointer operator->() const { return operator*(); }
609 SUnitIterator& operator++() { // Preincrement
613 SUnitIterator operator++(int) { // Postincrement
614 SUnitIterator tmp = *this; ++*this; return tmp;
617 static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); }
618 static SUnitIterator end (SUnit *N) {
619 return SUnitIterator(N, (unsigned)N->Preds.size());
622 unsigned getOperand() const { return Operand; }
623 const SUnit *getNode() const { return Node; }
624 /// isCtrlDep - Test if this is not an SDep::Data dependence.
625 bool isCtrlDep() const {
626 return getSDep().isCtrl();
628 bool isArtificialDep() const {
629 return getSDep().isArtificial();
631 const SDep &getSDep() const {
632 return Node->Preds[Operand];
636 template <> struct GraphTraits<SUnit*> {
637 typedef SUnit NodeType;
638 typedef SUnitIterator ChildIteratorType;
639 static inline NodeType *getEntryNode(SUnit *N) { return N; }
640 static inline ChildIteratorType child_begin(NodeType *N) {
641 return SUnitIterator::begin(N);
643 static inline ChildIteratorType child_end(NodeType *N) {
644 return SUnitIterator::end(N);
648 template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> {
649 typedef std::vector<SUnit>::iterator nodes_iterator;
650 static nodes_iterator nodes_begin(ScheduleDAG *G) {
651 return G->SUnits.begin();
653 static nodes_iterator nodes_end(ScheduleDAG *G) {
654 return G->SUnits.end();
658 /// ScheduleDAGTopologicalSort is a class that computes a topological
659 /// ordering for SUnits and provides methods for dynamically updating
660 /// the ordering as new edges are added.
662 /// This allows a very fast implementation of IsReachable, for example.
664 class ScheduleDAGTopologicalSort {
665 /// SUnits - A reference to the ScheduleDAG's SUnits.
666 std::vector<SUnit> &SUnits;
668 /// Index2Node - Maps topological index to the node number.
669 std::vector<int> Index2Node;
670 /// Node2Index - Maps the node number to its topological index.
671 std::vector<int> Node2Index;
672 /// Visited - a set of nodes visited during a DFS traversal.
675 /// DFS - make a DFS traversal and mark all nodes affected by the
676 /// edge insertion. These nodes will later get new topological indexes
677 /// by means of the Shift method.
678 void DFS(const SUnit *SU, int UpperBound, bool& HasLoop);
680 /// Shift - reassign topological indexes for the nodes in the DAG
681 /// to preserve the topological ordering.
682 void Shift(BitVector& Visited, int LowerBound, int UpperBound);
684 /// Allocate - assign the topological index to the node n.
685 void Allocate(int n, int index);
688 explicit ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits);
690 /// InitDAGTopologicalSorting - create the initial topological
691 /// ordering from the DAG to be scheduled.
692 void InitDAGTopologicalSorting();
694 /// IsReachable - Checks if SU is reachable from TargetSU.
695 bool IsReachable(const SUnit *SU, const SUnit *TargetSU);
697 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU
698 /// will create a cycle.
699 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU);
701 /// AddPred - Updates the topological ordering to accommodate an edge
702 /// to be added from SUnit X to SUnit Y.
703 void AddPred(SUnit *Y, SUnit *X);
705 /// RemovePred - Updates the topological ordering to accommodate an
706 /// an edge to be removed from the specified node N from the predecessors
707 /// of the current node M.
708 void RemovePred(SUnit *M, SUnit *N);
710 typedef std::vector<int>::iterator iterator;
711 typedef std::vector<int>::const_iterator const_iterator;
712 iterator begin() { return Index2Node.begin(); }
713 const_iterator begin() const { return Index2Node.begin(); }
714 iterator end() { return Index2Node.end(); }
715 const_iterator end() const { return Index2Node.end(); }
717 typedef std::vector<int>::reverse_iterator reverse_iterator;
718 typedef std::vector<int>::const_reverse_iterator const_reverse_iterator;
719 reverse_iterator rbegin() { return Index2Node.rbegin(); }
720 const_reverse_iterator rbegin() const { return Index2Node.rbegin(); }
721 reverse_iterator rend() { return Index2Node.rend(); }
722 const_reverse_iterator rend() const { return Index2Node.rend(); }