1 //===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAG class, which is used as the common
11 // base class for SelectionDAG-based instruction scheduler.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SCHEDULEDAG_H
16 #define LLVM_CODEGEN_SCHEDULEDAG_H
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/DenseMap.h"
22 #include "llvm/ADT/GraphTraits.h"
23 #include "llvm/ADT/SmallSet.h"
28 class MachineConstantPool;
29 class MachineFunction;
30 class MachineModuleInfo;
31 class MachineRegisterInfo;
33 class TargetRegisterInfo;
35 class SelectionDAGISel;
36 class TargetInstrInfo;
37 class TargetInstrDesc;
40 class TargetRegisterClass;
42 /// HazardRecognizer - This determines whether or not an instruction can be
43 /// issued this cycle, and whether or not a noop needs to be inserted to handle
45 class HazardRecognizer {
47 virtual ~HazardRecognizer();
50 NoHazard, // This instruction can be emitted at this cycle.
51 Hazard, // This instruction can't be emitted at this cycle.
52 NoopHazard // This instruction can't be emitted, and needs noops.
55 /// getHazardType - Return the hazard type of emitting this node. There are
56 /// three possible results. Either:
57 /// * NoHazard: it is legal to issue this instruction on this cycle.
58 /// * Hazard: issuing this instruction would stall the machine. If some
59 /// other instruction is available, issue it first.
60 /// * NoopHazard: issuing this instruction would break the program. If
61 /// some other instruction can be issued, do so, otherwise issue a noop.
62 virtual HazardType getHazardType(SDNode *) {
66 /// EmitInstruction - This callback is invoked when an instruction is
67 /// emitted, to advance the hazard state.
68 virtual void EmitInstruction(SDNode *) {}
70 /// AdvanceCycle - This callback is invoked when no instructions can be
71 /// issued on this cycle without a hazard. This should increment the
72 /// internal state of the hazard recognizer so that previously "Hazard"
73 /// instructions will now not be hazards.
74 virtual void AdvanceCycle() {}
76 /// EmitNoop - This callback is invoked when a noop was added to the
77 /// instruction stream.
78 virtual void EmitNoop() {}
81 /// SDep - Scheduling dependency. It keeps track of dependent nodes,
82 /// cost of the depdenency, etc.
84 SUnit *Dep; // Dependent - either a predecessor or a successor.
85 unsigned Reg; // If non-zero, this dep is a phy register dependency.
86 int Cost; // Cost of the dependency.
87 bool isCtrl : 1; // True iff it's a control dependency.
88 bool isSpecial : 1; // True iff it's a special ctrl dep added during sched.
89 SDep(SUnit *d, unsigned r, int t, bool c, bool s)
90 : Dep(d), Reg(r), Cost(t), isCtrl(c), isSpecial(s) {}
93 /// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
94 /// a group of nodes flagged together.
96 SDNode *Node; // Representative node.
97 SmallVector<SDNode*,4> FlaggedNodes;// All nodes flagged to Node.
98 unsigned InstanceNo; // Instance#. One SDNode can be multiple
99 // SUnit due to cloning.
101 // Preds/Succs - The SUnits before/after us in the graph. The boolean value
102 // is true if the edge is a token chain edge, false if it is a value edge.
103 SmallVector<SDep, 4> Preds; // All sunit predecessors.
104 SmallVector<SDep, 4> Succs; // All sunit successors.
106 typedef SmallVector<SDep, 4>::iterator pred_iterator;
107 typedef SmallVector<SDep, 4>::iterator succ_iterator;
108 typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator;
109 typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator;
111 unsigned NodeNum; // Entry # of node in the node vector.
112 unsigned NodeQueueId; // Queue id of node.
113 unsigned short Latency; // Node latency.
114 short NumPreds; // # of preds.
115 short NumSuccs; // # of sucss.
116 short NumPredsLeft; // # of preds not scheduled.
117 short NumSuccsLeft; // # of succs not scheduled.
118 bool isTwoAddress : 1; // Is a two-address instruction.
119 bool isCommutable : 1; // Is a commutable instruction.
120 bool hasPhysRegDefs : 1; // Has physreg defs that are being used.
121 bool isPending : 1; // True once pending.
122 bool isAvailable : 1; // True once available.
123 bool isScheduled : 1; // True once scheduled.
124 unsigned CycleBound; // Upper/lower cycle to be scheduled at.
125 unsigned Cycle; // Once scheduled, the cycle of the op.
126 unsigned Depth; // Node depth;
127 unsigned Height; // Node height;
128 const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null.
129 const TargetRegisterClass *CopySrcRC;
131 SUnit(SDNode *node, unsigned nodenum)
132 : Node(node), InstanceNo(0), NodeNum(nodenum), NodeQueueId(0), Latency(0),
133 NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
134 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
135 isPending(false), isAvailable(false), isScheduled(false),
136 CycleBound(0), Cycle(0), Depth(0), Height(0),
137 CopyDstRC(NULL), CopySrcRC(NULL) {}
139 /// addPred - This adds the specified node as a pred of the current node if
140 /// not already. This returns true if this is a new pred.
141 bool addPred(SUnit *N, bool isCtrl, bool isSpecial,
142 unsigned PhyReg = 0, int Cost = 1) {
143 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
144 if (Preds[i].Dep == N &&
145 Preds[i].isCtrl == isCtrl && Preds[i].isSpecial == isSpecial)
147 Preds.push_back(SDep(N, PhyReg, Cost, isCtrl, isSpecial));
148 N->Succs.push_back(SDep(this, PhyReg, Cost, isCtrl, isSpecial));
160 bool removePred(SUnit *N, bool isCtrl, bool isSpecial) {
161 for (SmallVector<SDep, 4>::iterator I = Preds.begin(), E = Preds.end();
163 if (I->Dep == N && I->isCtrl == isCtrl && I->isSpecial == isSpecial) {
164 bool FoundSucc = false;
165 for (SmallVector<SDep, 4>::iterator II = N->Succs.begin(),
166 EE = N->Succs.end(); II != EE; ++II)
167 if (II->Dep == this &&
168 II->isCtrl == isCtrl && II->isSpecial == isSpecial) {
173 assert(FoundSucc && "Mismatching preds / succs lists!");
188 bool isPred(SUnit *N) {
189 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
190 if (Preds[i].Dep == N)
195 bool isSucc(SUnit *N) {
196 for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i)
197 if (Succs[i].Dep == N)
202 void dump(const SelectionDAG *G) const;
203 void dumpAll(const SelectionDAG *G) const;
206 //===--------------------------------------------------------------------===//
207 /// SchedulingPriorityQueue - This interface is used to plug different
208 /// priorities computation algorithms into the list scheduler. It implements
209 /// the interface of a standard priority queue, where nodes are inserted in
210 /// arbitrary order and returned in priority order. The computation of the
211 /// priority and the representation of the queue are totally up to the
212 /// implementation to decide.
214 class SchedulingPriorityQueue {
216 virtual ~SchedulingPriorityQueue() {}
218 virtual void initNodes(DenseMap<SDNode*, std::vector<SUnit*> > &SUMap,
219 std::vector<SUnit> &SUnits) = 0;
220 virtual void addNode(const SUnit *SU) = 0;
221 virtual void updateNode(const SUnit *SU) = 0;
222 virtual void releaseState() = 0;
224 virtual unsigned size() const = 0;
225 virtual bool empty() const = 0;
226 virtual void push(SUnit *U) = 0;
228 virtual void push_all(const std::vector<SUnit *> &Nodes) = 0;
229 virtual SUnit *pop() = 0;
231 virtual void remove(SUnit *SU) = 0;
233 /// ScheduledNode - As each node is scheduled, this method is invoked. This
234 /// allows the priority function to adjust the priority of node that have
235 /// already been emitted.
236 virtual void ScheduledNode(SUnit *) {}
238 virtual void UnscheduledNode(SUnit *) {}
243 SelectionDAG &DAG; // DAG of the current basic block
244 MachineBasicBlock *BB; // Current basic block
245 const TargetMachine &TM; // Target processor
246 const TargetInstrInfo *TII; // Target instruction information
247 const TargetRegisterInfo *TRI; // Target processor register info
248 TargetLowering *TLI; // Target lowering info
249 MachineFunction *MF; // Machine function
250 MachineRegisterInfo &MRI; // Virtual/real register map
251 MachineConstantPool *ConstPool; // Target constant pool
252 std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s
253 // represent noop instructions.
254 DenseMap<SDNode*, std::vector<SUnit*> > SUnitMap;
255 // SDNode to SUnit mapping (n -> n).
256 std::vector<SUnit> SUnits; // The scheduling units.
257 SmallSet<SDNode*, 16> CommuteSet; // Nodes that should be commuted.
259 ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb,
260 const TargetMachine &tm);
262 virtual ~ScheduleDAG() {}
264 /// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered
269 /// Run - perform scheduling.
271 MachineBasicBlock *Run();
273 /// isPassiveNode - Return true if the node is a non-scheduled leaf.
275 static bool isPassiveNode(SDNode *Node) {
276 if (isa<ConstantSDNode>(Node)) return true;
277 if (isa<ConstantFPSDNode>(Node)) return true;
278 if (isa<RegisterSDNode>(Node)) return true;
279 if (isa<GlobalAddressSDNode>(Node)) return true;
280 if (isa<BasicBlockSDNode>(Node)) return true;
281 if (isa<FrameIndexSDNode>(Node)) return true;
282 if (isa<ConstantPoolSDNode>(Node)) return true;
283 if (isa<JumpTableSDNode>(Node)) return true;
284 if (isa<ExternalSymbolSDNode>(Node)) return true;
285 if (isa<MemOperandSDNode>(Node)) return true;
286 if (Node->getOpcode() == ISD::EntryToken) return true;
290 /// NewSUnit - Creates a new SUnit and return a ptr to it.
292 SUnit *NewSUnit(SDNode *N) {
293 SUnits.push_back(SUnit(N, (unsigned)SUnits.size()));
294 return &SUnits.back();
297 /// Clone - Creates a clone of the specified SUnit. It does not copy the
298 /// predecessors / successors info nor the temporary scheduling states.
299 SUnit *Clone(SUnit *N);
301 /// BuildSchedUnits - Build SUnits from the selection dag that we are input.
302 /// This SUnit graph is similar to the SelectionDAG, but represents flagged
303 /// together nodes with a single SUnit.
304 void BuildSchedUnits();
306 /// ComputeLatency - Compute node latency.
308 void ComputeLatency(SUnit *SU);
310 /// CalculateDepths, CalculateHeights - Calculate node depth / height.
312 void CalculateDepths();
313 void CalculateHeights();
315 /// CountResults - The results of target nodes have register or immediate
316 /// operands first, then an optional chain, and optional flag operands
317 /// (which do not go into the machine instrs.)
318 static unsigned CountResults(SDNode *Node);
320 /// CountOperands - The inputs to target nodes have any actual inputs first,
321 /// followed by special operands that describe memory references, then an
322 /// optional chain operand, then flag operands. Compute the number of
323 /// actual operands that will go into the resulting MachineInstr.
324 static unsigned CountOperands(SDNode *Node);
326 /// ComputeMemOperandsEnd - Find the index one past the last
327 /// MemOperandSDNode operand
328 static unsigned ComputeMemOperandsEnd(SDNode *Node);
330 /// EmitNode - Generate machine code for an node and needed dependencies.
331 /// VRBaseMap contains, for each already emitted node, the first virtual
332 /// register number for the results of the node.
334 void EmitNode(SDNode *Node, unsigned InstNo,
335 DenseMap<SDOperand, unsigned> &VRBaseMap);
337 /// EmitNoop - Emit a noop instruction.
343 void dumpSchedule() const;
345 /// Schedule - Order nodes according to selected style.
347 virtual void Schedule() {}
350 /// EmitSubregNode - Generate machine code for subreg nodes.
352 void EmitSubregNode(SDNode *Node,
353 DenseMap<SDOperand, unsigned> &VRBaseMap);
355 /// getVR - Return the virtual register corresponding to the specified result
356 /// of the specified node.
357 unsigned getVR(SDOperand Op, DenseMap<SDOperand, unsigned> &VRBaseMap);
359 /// getDstOfCopyToRegUse - If the only use of the specified result number of
360 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
361 unsigned getDstOfOnlyCopyToRegUse(SDNode *Node, unsigned ResNo) const;
363 void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum,
364 const TargetInstrDesc *II,
365 DenseMap<SDOperand, unsigned> &VRBaseMap);
367 void AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO);
369 void EmitCrossRCCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap);
371 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
372 /// implicit physical register output.
373 void EmitCopyFromReg(SDNode *Node, unsigned ResNo, unsigned InstNo,
375 DenseMap<SDOperand, unsigned> &VRBaseMap);
377 void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
378 const TargetInstrDesc &II,
379 DenseMap<SDOperand, unsigned> &VRBaseMap);
381 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
382 /// physical register has only a single copy use, then coalesced the copy
384 void EmitLiveInCopy(MachineBasicBlock *MBB,
385 MachineBasicBlock::iterator &InsertPos,
386 unsigned VirtReg, unsigned PhysReg,
387 const TargetRegisterClass *RC,
388 DenseMap<MachineInstr*, unsigned> &CopyRegMap);
390 /// EmitLiveInCopies - If this is the first basic block in the function,
391 /// and if it has live ins that need to be copied into vregs, emit the
392 /// copies into the top of the block.
393 void EmitLiveInCopies(MachineBasicBlock *MBB);
396 /// createBURRListDAGScheduler - This creates a bottom up register usage
397 /// reduction list scheduler.
398 ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS,
400 MachineBasicBlock *BB);
402 /// createTDRRListDAGScheduler - This creates a top down register usage
403 /// reduction list scheduler.
404 ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS,
406 MachineBasicBlock *BB);
408 /// createTDListDAGScheduler - This creates a top-down list scheduler with
409 /// a hazard recognizer.
410 ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS,
412 MachineBasicBlock *BB);
414 /// createDefaultScheduler - This creates an instruction scheduler appropriate
416 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
418 MachineBasicBlock *BB);
420 class SUnitIterator : public forward_iterator<SUnit, ptrdiff_t> {
424 SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {}
426 bool operator==(const SUnitIterator& x) const {
427 return Operand == x.Operand;
429 bool operator!=(const SUnitIterator& x) const { return !operator==(x); }
431 const SUnitIterator &operator=(const SUnitIterator &I) {
432 assert(I.Node == Node && "Cannot assign iterators to two different nodes!");
437 pointer operator*() const {
438 return Node->Preds[Operand].Dep;
440 pointer operator->() const { return operator*(); }
442 SUnitIterator& operator++() { // Preincrement
446 SUnitIterator operator++(int) { // Postincrement
447 SUnitIterator tmp = *this; ++*this; return tmp;
450 static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); }
451 static SUnitIterator end (SUnit *N) {
452 return SUnitIterator(N, (unsigned)N->Preds.size());
455 unsigned getOperand() const { return Operand; }
456 const SUnit *getNode() const { return Node; }
457 bool isCtrlDep() const { return Node->Preds[Operand].isCtrl; }
458 bool isSpecialDep() const { return Node->Preds[Operand].isSpecial; }
461 template <> struct GraphTraits<SUnit*> {
462 typedef SUnit NodeType;
463 typedef SUnitIterator ChildIteratorType;
464 static inline NodeType *getEntryNode(SUnit *N) { return N; }
465 static inline ChildIteratorType child_begin(NodeType *N) {
466 return SUnitIterator::begin(N);
468 static inline ChildIteratorType child_end(NodeType *N) {
469 return SUnitIterator::end(N);
473 template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> {
474 typedef std::vector<SUnit>::iterator nodes_iterator;
475 static nodes_iterator nodes_begin(ScheduleDAG *G) {
476 return G->SUnits.begin();
478 static nodes_iterator nodes_end(ScheduleDAG *G) {
479 return G->SUnits.end();