1 //===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAG class, which is used as the common
11 // base class for instruction schedulers. This encapsulates the scheduling DAG,
12 // which is shared between SelectionDAG and MachineInstr scheduling.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_SCHEDULEDAG_H
17 #define LLVM_CODEGEN_SCHEDULEDAG_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/ADT/DenseMap.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/GraphTraits.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/ADT/PointerIntPair.h"
30 class MachineConstantPool;
31 class MachineFunction;
32 class MachineRegisterInfo;
34 class TargetRegisterInfo;
37 class TargetInstrInfo;
40 class TargetRegisterClass;
41 template<class Graph> class GraphWriter;
43 /// SDep - Scheduling dependency. This represents one direction of an
44 /// edge in the scheduling DAG.
47 /// Kind - These are the different kinds of scheduling dependencies.
49 Data, ///< Regular data dependence (aka true-dependence).
50 Anti, ///< A register anti-dependedence (aka WAR).
51 Output, ///< A register output-dependence (aka WAW).
52 Order ///< Any other ordering dependency.
56 /// Dep - A pointer to the depending/depended-on SUnit, and an enum
57 /// indicating the kind of the dependency.
58 PointerIntPair<SUnit *, 2, Kind> Dep;
60 /// Contents - A union discriminated by the dependence kind.
62 /// Reg - For Data, Anti, and Output dependencies, the associated
63 /// register. For Data dependencies that don't currently have a register
64 /// assigned, this is set to zero.
67 /// Order - Additional information about Order dependencies.
69 /// isNormalMemory - True if both sides of the dependence
70 /// access memory in non-volatile and fully modeled ways.
71 bool isNormalMemory : 1;
73 /// isMustAlias - True if both sides of the dependence are known to
74 /// access the same memory.
77 /// isArtificial - True if this is an artificial dependency, meaning
78 /// it is not necessary for program correctness, and may be safely
79 /// deleted if necessary.
80 bool isArtificial : 1;
84 /// Latency - The time associated with this edge. Often this is just
85 /// the value of the Latency field of the predecessor, however advanced
86 /// models may provide additional information about specific edges.
88 /// Record MinLatency seperately from "expected" Latency.
92 /// SDep - Construct a null SDep. This is only for use by container
93 /// classes which require default constructors. SUnits may not
94 /// have null SDep edges.
95 SDep() : Dep(0, Data) {}
97 /// SDep - Construct an SDep with the specified values.
98 SDep(SUnit *S, Kind kind, unsigned latency = 1, unsigned Reg = 0,
99 bool isNormalMemory = false, bool isMustAlias = false,
100 bool isArtificial = false)
101 : Dep(S, kind), Contents(), Latency(latency), MinLatency(latency) {
106 "SDep::Anti and SDep::Output must use a non-zero Reg!");
109 assert(!isMustAlias && "isMustAlias only applies with SDep::Order!");
110 assert(!isArtificial && "isArtificial only applies with SDep::Order!");
114 assert(Reg == 0 && "Reg given for non-register dependence!");
115 Contents.Order.isNormalMemory = isNormalMemory;
116 Contents.Order.isMustAlias = isMustAlias;
117 Contents.Order.isArtificial = isArtificial;
122 /// Return true if the specified SDep is equivalent except for latency.
123 bool overlaps(const SDep &Other) const {
124 if (Dep != Other.Dep) return false;
125 switch (Dep.getInt()) {
129 return Contents.Reg == Other.Contents.Reg;
131 return Contents.Order.isNormalMemory ==
132 Other.Contents.Order.isNormalMemory &&
133 Contents.Order.isMustAlias == Other.Contents.Order.isMustAlias &&
134 Contents.Order.isArtificial == Other.Contents.Order.isArtificial;
136 llvm_unreachable("Invalid dependency kind!");
139 bool operator==(const SDep &Other) const {
140 return overlaps(Other)
141 && Latency == Other.Latency && MinLatency == Other.MinLatency;
144 bool operator!=(const SDep &Other) const {
145 return !operator==(Other);
148 /// getLatency - Return the latency value for this edge, which roughly
149 /// means the minimum number of cycles that must elapse between the
150 /// predecessor and the successor, given that they have this edge
152 unsigned getLatency() const {
156 /// setLatency - Set the latency for this edge.
157 void setLatency(unsigned Lat) {
161 /// getMinLatency - Return the minimum latency for this edge. Minimum
162 /// latency is used for scheduling groups, while normal (expected) latency
163 /// is for instruction cost and critical path.
164 unsigned getMinLatency() const {
168 /// setMinLatency - Set the minimum latency for this edge.
169 void setMinLatency(unsigned Lat) {
173 //// getSUnit - Return the SUnit to which this edge points.
174 SUnit *getSUnit() const {
175 return Dep.getPointer();
178 //// setSUnit - Assign the SUnit to which this edge points.
179 void setSUnit(SUnit *SU) {
183 /// getKind - Return an enum value representing the kind of the dependence.
184 Kind getKind() const {
188 /// isCtrl - Shorthand for getKind() != SDep::Data.
189 bool isCtrl() const {
190 return getKind() != Data;
193 /// isNormalMemory - Test if this is an Order dependence between two
194 /// memory accesses where both sides of the dependence access memory
195 /// in non-volatile and fully modeled ways.
196 bool isNormalMemory() const {
197 return getKind() == Order && Contents.Order.isNormalMemory;
200 /// isMustAlias - Test if this is an Order dependence that is marked
201 /// as "must alias", meaning that the SUnits at either end of the edge
202 /// have a memory dependence on a known memory location.
203 bool isMustAlias() const {
204 return getKind() == Order && Contents.Order.isMustAlias;
207 /// isArtificial - Test if this is an Order dependence that is marked
208 /// as "artificial", meaning it isn't necessary for correctness.
209 bool isArtificial() const {
210 return getKind() == Order && Contents.Order.isArtificial;
213 /// isAssignedRegDep - Test if this is a Data dependence that is
214 /// associated with a register.
215 bool isAssignedRegDep() const {
216 return getKind() == Data && Contents.Reg != 0;
219 /// getReg - Return the register associated with this edge. This is
220 /// only valid on Data, Anti, and Output edges. On Data edges, this
221 /// value may be zero, meaning there is no associated register.
222 unsigned getReg() const {
223 assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
224 "getReg called on non-register dependence edge!");
228 /// setReg - Assign the associated register for this edge. This is
229 /// only valid on Data, Anti, and Output edges. On Anti and Output
230 /// edges, this value must not be zero. On Data edges, the value may
231 /// be zero, which would mean that no specific register is associated
233 void setReg(unsigned Reg) {
234 assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
235 "setReg called on non-register dependence edge!");
236 assert((getKind() != Anti || Reg != 0) &&
237 "SDep::Anti edge cannot use the zero register!");
238 assert((getKind() != Output || Reg != 0) &&
239 "SDep::Output edge cannot use the zero register!");
245 struct isPodLike<SDep> { static const bool value = true; };
247 /// SUnit - Scheduling unit. This is a node in the scheduling DAG.
250 SDNode *Node; // Representative node.
251 MachineInstr *Instr; // Alternatively, a MachineInstr.
253 SUnit *OrigNode; // If not this, the node from which
254 // this node was cloned.
255 // (SD scheduling only)
257 // Preds/Succs - The SUnits before/after us in the graph.
258 SmallVector<SDep, 4> Preds; // All sunit predecessors.
259 SmallVector<SDep, 4> Succs; // All sunit successors.
261 typedef SmallVector<SDep, 4>::iterator pred_iterator;
262 typedef SmallVector<SDep, 4>::iterator succ_iterator;
263 typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator;
264 typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator;
266 unsigned NodeNum; // Entry # of node in the node vector.
267 unsigned NodeQueueId; // Queue id of node.
268 unsigned NumPreds; // # of SDep::Data preds.
269 unsigned NumSuccs; // # of SDep::Data sucss.
270 unsigned NumPredsLeft; // # of preds not scheduled.
271 unsigned NumSuccsLeft; // # of succs not scheduled.
272 unsigned short NumRegDefsLeft; // # of reg defs with no scheduled use.
273 unsigned short Latency; // Node latency.
274 bool isVRegCycle : 1; // May use and def the same vreg.
275 bool isCall : 1; // Is a function call.
276 bool isCallOp : 1; // Is a function call operand.
277 bool isTwoAddress : 1; // Is a two-address instruction.
278 bool isCommutable : 1; // Is a commutable instruction.
279 bool hasPhysRegDefs : 1; // Has physreg defs that are being used.
280 bool hasPhysRegClobbers : 1; // Has any physreg defs, used or not.
281 bool isPending : 1; // True once pending.
282 bool isAvailable : 1; // True once available.
283 bool isScheduled : 1; // True once scheduled.
284 bool isScheduleHigh : 1; // True if preferable to schedule high.
285 bool isScheduleLow : 1; // True if preferable to schedule low.
286 bool isCloned : 1; // True if this node has been cloned.
287 Sched::Preference SchedulingPref; // Scheduling preference.
290 bool isDepthCurrent : 1; // True if Depth is current.
291 bool isHeightCurrent : 1; // True if Height is current.
292 unsigned Depth; // Node depth.
293 unsigned Height; // Node height.
295 unsigned TopReadyCycle; // Cycle relative to start when node is ready.
296 unsigned BotReadyCycle; // Cycle relative to end when node is ready.
298 const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null.
299 const TargetRegisterClass *CopySrcRC;
301 /// SUnit - Construct an SUnit for pre-regalloc scheduling to represent
302 /// an SDNode and any nodes flagged to it.
303 SUnit(SDNode *node, unsigned nodenum)
304 : Node(node), Instr(0), OrigNode(0), NodeNum(nodenum),
305 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
306 NumSuccsLeft(0), NumRegDefsLeft(0), Latency(0),
307 isVRegCycle(false), isCall(false), isCallOp(false), isTwoAddress(false),
308 isCommutable(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
309 isPending(false), isAvailable(false), isScheduled(false),
310 isScheduleHigh(false), isScheduleLow(false), isCloned(false),
311 SchedulingPref(Sched::None),
312 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
313 TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {}
315 /// SUnit - Construct an SUnit for post-regalloc scheduling to represent
317 SUnit(MachineInstr *instr, unsigned nodenum)
318 : Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum),
319 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
320 NumSuccsLeft(0), NumRegDefsLeft(0), Latency(0),
321 isVRegCycle(false), isCall(false), isCallOp(false), isTwoAddress(false),
322 isCommutable(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
323 isPending(false), isAvailable(false), isScheduled(false),
324 isScheduleHigh(false), isScheduleLow(false), isCloned(false),
325 SchedulingPref(Sched::None),
326 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
327 TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {}
329 /// SUnit - Construct a placeholder SUnit.
331 : Node(0), Instr(0), OrigNode(0), NodeNum(~0u),
332 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
333 NumSuccsLeft(0), NumRegDefsLeft(0), Latency(0),
334 isVRegCycle(false), isCall(false), isCallOp(false), isTwoAddress(false),
335 isCommutable(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
336 isPending(false), isAvailable(false), isScheduled(false),
337 isScheduleHigh(false), isScheduleLow(false), isCloned(false),
338 SchedulingPref(Sched::None),
339 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
340 TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {}
342 /// setNode - Assign the representative SDNode for this SUnit.
343 /// This may be used during pre-regalloc scheduling.
344 void setNode(SDNode *N) {
345 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!");
349 /// getNode - Return the representative SDNode for this SUnit.
350 /// This may be used during pre-regalloc scheduling.
351 SDNode *getNode() const {
352 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!");
356 /// isInstr - Return true if this SUnit refers to a machine instruction as
357 /// opposed to an SDNode.
358 bool isInstr() const { return Instr; }
360 /// setInstr - Assign the instruction for the SUnit.
361 /// This may be used during post-regalloc scheduling.
362 void setInstr(MachineInstr *MI) {
363 assert(!Node && "Setting MachineInstr of SUnit with SDNode!");
367 /// getInstr - Return the representative MachineInstr for this SUnit.
368 /// This may be used during post-regalloc scheduling.
369 MachineInstr *getInstr() const {
370 assert(!Node && "Reading MachineInstr of SUnit with SDNode!");
374 /// addPred - This adds the specified edge as a pred of the current node if
375 /// not already. It also adds the current node as a successor of the
377 bool addPred(const SDep &D);
379 /// removePred - This removes the specified edge as a pred of the current
380 /// node if it exists. It also removes the current node as a successor of
381 /// the specified node.
382 void removePred(const SDep &D);
384 /// getDepth - Return the depth of this node, which is the length of the
385 /// maximum path up to any node which has no predecessors.
386 unsigned getDepth() const {
388 const_cast<SUnit *>(this)->ComputeDepth();
392 /// getHeight - Return the height of this node, which is the length of the
393 /// maximum path down to any node which has no successors.
394 unsigned getHeight() const {
395 if (!isHeightCurrent)
396 const_cast<SUnit *>(this)->ComputeHeight();
400 /// setDepthToAtLeast - If NewDepth is greater than this node's
401 /// depth value, set it to be the new depth value. This also
402 /// recursively marks successor nodes dirty.
403 void setDepthToAtLeast(unsigned NewDepth);
405 /// setDepthToAtLeast - If NewDepth is greater than this node's
406 /// depth value, set it to be the new height value. This also
407 /// recursively marks predecessor nodes dirty.
408 void setHeightToAtLeast(unsigned NewHeight);
410 /// setDepthDirty - Set a flag in this node to indicate that its
411 /// stored Depth value will require recomputation the next time
412 /// getDepth() is called.
413 void setDepthDirty();
415 /// setHeightDirty - Set a flag in this node to indicate that its
416 /// stored Height value will require recomputation the next time
417 /// getHeight() is called.
418 void setHeightDirty();
420 /// isPred - Test if node N is a predecessor of this node.
421 bool isPred(SUnit *N) {
422 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
423 if (Preds[i].getSUnit() == N)
428 /// isSucc - Test if node N is a successor of this node.
429 bool isSucc(SUnit *N) {
430 for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i)
431 if (Succs[i].getSUnit() == N)
436 bool isTopReady() const {
437 return NumPredsLeft == 0;
439 bool isBottomReady() const {
440 return NumSuccsLeft == 0;
443 void dump(const ScheduleDAG *G) const;
444 void dumpAll(const ScheduleDAG *G) const;
445 void print(raw_ostream &O, const ScheduleDAG *G) const;
449 void ComputeHeight();
452 //===--------------------------------------------------------------------===//
453 /// SchedulingPriorityQueue - This interface is used to plug different
454 /// priorities computation algorithms into the list scheduler. It implements
455 /// the interface of a standard priority queue, where nodes are inserted in
456 /// arbitrary order and returned in priority order. The computation of the
457 /// priority and the representation of the queue are totally up to the
458 /// implementation to decide.
460 class SchedulingPriorityQueue {
461 virtual void anchor();
465 SchedulingPriorityQueue(bool rf = false):
466 CurCycle(0), HasReadyFilter(rf) {}
467 virtual ~SchedulingPriorityQueue() {}
469 virtual bool isBottomUp() const = 0;
471 virtual void initNodes(std::vector<SUnit> &SUnits) = 0;
472 virtual void addNode(const SUnit *SU) = 0;
473 virtual void updateNode(const SUnit *SU) = 0;
474 virtual void releaseState() = 0;
476 virtual bool empty() const = 0;
478 bool hasReadyFilter() const { return HasReadyFilter; }
480 virtual bool tracksRegPressure() const { return false; }
482 virtual bool isReady(SUnit *) const {
483 assert(!HasReadyFilter && "The ready filter must override isReady()");
486 virtual void push(SUnit *U) = 0;
488 void push_all(const std::vector<SUnit *> &Nodes) {
489 for (std::vector<SUnit *>::const_iterator I = Nodes.begin(),
490 E = Nodes.end(); I != E; ++I)
494 virtual SUnit *pop() = 0;
496 virtual void remove(SUnit *SU) = 0;
498 virtual void dump(ScheduleDAG *) const {}
500 /// scheduledNode - As each node is scheduled, this method is invoked. This
501 /// allows the priority function to adjust the priority of related
502 /// unscheduled nodes, for example.
504 virtual void scheduledNode(SUnit *) {}
506 virtual void unscheduledNode(SUnit *) {}
508 void setCurCycle(unsigned Cycle) {
512 unsigned getCurCycle() const {
519 const TargetMachine &TM; // Target processor
520 const TargetInstrInfo *TII; // Target instruction information
521 const TargetRegisterInfo *TRI; // Target processor register info
522 MachineFunction &MF; // Machine function
523 MachineRegisterInfo &MRI; // Virtual/real register map
524 std::vector<SUnit> SUnits; // The scheduling units.
525 SUnit EntrySU; // Special node for the region entry.
526 SUnit ExitSU; // Special node for the region exit.
529 static const bool StressSched = false;
534 explicit ScheduleDAG(MachineFunction &mf);
536 virtual ~ScheduleDAG();
538 /// clearDAG - clear the DAG state (between regions).
541 /// getInstrDesc - Return the MCInstrDesc of this SUnit.
542 /// Return NULL for SDNodes without a machine opcode.
543 const MCInstrDesc *getInstrDesc(const SUnit *SU) const {
544 if (SU->isInstr()) return &SU->getInstr()->getDesc();
545 return getNodeDesc(SU->getNode());
548 /// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered
551 void viewGraph(const Twine &Name, const Twine &Title);
554 virtual void dumpNode(const SUnit *SU) const = 0;
556 /// getGraphNodeLabel - Return a label for an SUnit node in a visualization
557 /// of the ScheduleDAG.
558 virtual std::string getGraphNodeLabel(const SUnit *SU) const = 0;
560 /// getDAGLabel - Return a label for the region of code covered by the DAG.
561 virtual std::string getDAGName() const = 0;
563 /// addCustomGraphFeatures - Add custom features for a visualization of
565 virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {}
568 /// VerifyScheduledDAG - Verify that all SUnits were scheduled and that
569 /// their state is consistent. Return the number of scheduled SUnits.
570 unsigned VerifyScheduledDAG(bool isBottomUp);
574 /// ComputeLatency - Compute node latency.
576 virtual void computeLatency(SUnit *SU) = 0;
578 /// ForceUnitLatencies - Return true if all scheduling edges should be given
579 /// a latency value of one. The default is to return false; schedulers may
580 /// override this as needed.
581 virtual bool forceUnitLatencies() const { return false; }
584 // Return the MCInstrDesc of this SDNode or NULL.
585 const MCInstrDesc *getNodeDesc(const SDNode *Node) const;
588 class SUnitIterator : public std::iterator<std::forward_iterator_tag,
593 SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {}
595 bool operator==(const SUnitIterator& x) const {
596 return Operand == x.Operand;
598 bool operator!=(const SUnitIterator& x) const { return !operator==(x); }
600 const SUnitIterator &operator=(const SUnitIterator &I) {
601 assert(I.Node==Node && "Cannot assign iterators to two different nodes!");
606 pointer operator*() const {
607 return Node->Preds[Operand].getSUnit();
609 pointer operator->() const { return operator*(); }
611 SUnitIterator& operator++() { // Preincrement
615 SUnitIterator operator++(int) { // Postincrement
616 SUnitIterator tmp = *this; ++*this; return tmp;
619 static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); }
620 static SUnitIterator end (SUnit *N) {
621 return SUnitIterator(N, (unsigned)N->Preds.size());
624 unsigned getOperand() const { return Operand; }
625 const SUnit *getNode() const { return Node; }
626 /// isCtrlDep - Test if this is not an SDep::Data dependence.
627 bool isCtrlDep() const {
628 return getSDep().isCtrl();
630 bool isArtificialDep() const {
631 return getSDep().isArtificial();
633 const SDep &getSDep() const {
634 return Node->Preds[Operand];
638 template <> struct GraphTraits<SUnit*> {
639 typedef SUnit NodeType;
640 typedef SUnitIterator ChildIteratorType;
641 static inline NodeType *getEntryNode(SUnit *N) { return N; }
642 static inline ChildIteratorType child_begin(NodeType *N) {
643 return SUnitIterator::begin(N);
645 static inline ChildIteratorType child_end(NodeType *N) {
646 return SUnitIterator::end(N);
650 template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> {
651 typedef std::vector<SUnit>::iterator nodes_iterator;
652 static nodes_iterator nodes_begin(ScheduleDAG *G) {
653 return G->SUnits.begin();
655 static nodes_iterator nodes_end(ScheduleDAG *G) {
656 return G->SUnits.end();
660 /// ScheduleDAGTopologicalSort is a class that computes a topological
661 /// ordering for SUnits and provides methods for dynamically updating
662 /// the ordering as new edges are added.
664 /// This allows a very fast implementation of IsReachable, for example.
666 class ScheduleDAGTopologicalSort {
667 /// SUnits - A reference to the ScheduleDAG's SUnits.
668 std::vector<SUnit> &SUnits;
670 /// Index2Node - Maps topological index to the node number.
671 std::vector<int> Index2Node;
672 /// Node2Index - Maps the node number to its topological index.
673 std::vector<int> Node2Index;
674 /// Visited - a set of nodes visited during a DFS traversal.
677 /// DFS - make a DFS traversal and mark all nodes affected by the
678 /// edge insertion. These nodes will later get new topological indexes
679 /// by means of the Shift method.
680 void DFS(const SUnit *SU, int UpperBound, bool& HasLoop);
682 /// Shift - reassign topological indexes for the nodes in the DAG
683 /// to preserve the topological ordering.
684 void Shift(BitVector& Visited, int LowerBound, int UpperBound);
686 /// Allocate - assign the topological index to the node n.
687 void Allocate(int n, int index);
690 explicit ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits);
692 /// InitDAGTopologicalSorting - create the initial topological
693 /// ordering from the DAG to be scheduled.
694 void InitDAGTopologicalSorting();
696 /// IsReachable - Checks if SU is reachable from TargetSU.
697 bool IsReachable(const SUnit *SU, const SUnit *TargetSU);
699 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU
700 /// will create a cycle.
701 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU);
703 /// AddPred - Updates the topological ordering to accommodate an edge
704 /// to be added from SUnit X to SUnit Y.
705 void AddPred(SUnit *Y, SUnit *X);
707 /// RemovePred - Updates the topological ordering to accommodate an
708 /// an edge to be removed from the specified node N from the predecessors
709 /// of the current node M.
710 void RemovePred(SUnit *M, SUnit *N);
712 typedef std::vector<int>::iterator iterator;
713 typedef std::vector<int>::const_iterator const_iterator;
714 iterator begin() { return Index2Node.begin(); }
715 const_iterator begin() const { return Index2Node.begin(); }
716 iterator end() { return Index2Node.end(); }
717 const_iterator end() const { return Index2Node.end(); }
719 typedef std::vector<int>::reverse_iterator reverse_iterator;
720 typedef std::vector<int>::const_reverse_iterator const_reverse_iterator;
721 reverse_iterator rbegin() { return Index2Node.rbegin(); }
722 const_reverse_iterator rbegin() const { return Index2Node.rbegin(); }
723 reverse_iterator rend() { return Index2Node.rend(); }
724 const_reverse_iterator rend() const { return Index2Node.rend(); }