1 //===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAG class, which is used as the common
11 // base class for instruction schedulers. This encapsulates the scheduling DAG,
12 // which is shared between SelectionDAG and MachineInstr scheduling.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_SCHEDULEDAG_H
17 #define LLVM_CODEGEN_SCHEDULEDAG_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/ADT/DenseMap.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/GraphTraits.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/ADT/PointerIntPair.h"
30 class MachineConstantPool;
31 class MachineFunction;
32 class MachineRegisterInfo;
34 struct MCSchedClassDesc;
35 class TargetRegisterInfo;
38 class TargetInstrInfo;
41 class TargetRegisterClass;
42 template<class Graph> class GraphWriter;
44 /// SDep - Scheduling dependency. This represents one direction of an
45 /// edge in the scheduling DAG.
48 /// Kind - These are the different kinds of scheduling dependencies.
50 Data, ///< Regular data dependence (aka true-dependence).
51 Anti, ///< A register anti-dependedence (aka WAR).
52 Output, ///< A register output-dependence (aka WAW).
53 Order ///< Any other ordering dependency.
57 Barrier, ///< An unknown scheduling barrier.
58 MayAliasMem, ///< Nonvolatile load/Store instructions that may alias.
59 MustAliasMem, ///< Nonvolatile load/Store instructions that must alias.
60 Artificial, ///< Arbitrary weak DAG edge (no actual dependence).
61 Cluster ///< Weak DAG edge linking a chain of clustered instrs.
65 /// Dep - A pointer to the depending/depended-on SUnit, and an enum
66 /// indicating the kind of the dependency.
67 PointerIntPair<SUnit *, 2, Kind> Dep;
69 /// Contents - A union discriminated by the dependence kind.
71 /// Reg - For Data, Anti, and Output dependencies, the associated
72 /// register. For Data dependencies that don't currently have a register
73 /// assigned, this is set to zero.
76 /// Order - Additional information about Order dependencies.
77 unsigned OrdKind; // enum OrderKind
80 /// Latency - The time associated with this edge. Often this is just
81 /// the value of the Latency field of the predecessor, however advanced
82 /// models may provide additional information about specific edges.
84 /// Record MinLatency seperately from "expected" Latency.
86 /// FIXME: this field is not packed on LP64. Convert to 16-bit DAG edge
87 /// latency after introducing saturating truncation.
91 /// SDep - Construct a null SDep. This is only for use by container
92 /// classes which require default constructors. SUnits may not
93 /// have null SDep edges.
94 SDep() : Dep(0, Data) {}
96 /// SDep - Construct an SDep with the specified values.
97 SDep(SUnit *S, Kind kind, unsigned Reg)
98 : Dep(S, kind), Contents() {
101 llvm_unreachable("Reg given for non-register dependence!");
105 "SDep::Anti and SDep::Output must use a non-zero Reg!");
114 MinLatency = Latency;
116 SDep(SUnit *S, OrderKind kind)
117 : Dep(S, Order), Contents(), Latency(0), MinLatency(0) {
118 Contents.OrdKind = kind;
121 /// Return true if the specified SDep is equivalent except for latency.
122 bool overlaps(const SDep &Other) const {
123 if (Dep != Other.Dep) return false;
124 switch (Dep.getInt()) {
128 return Contents.Reg == Other.Contents.Reg;
130 return Contents.OrdKind == Other.Contents.OrdKind;
132 llvm_unreachable("Invalid dependency kind!");
135 bool operator==(const SDep &Other) const {
136 return overlaps(Other)
137 && Latency == Other.Latency && MinLatency == Other.MinLatency;
140 bool operator!=(const SDep &Other) const {
141 return !operator==(Other);
144 /// getLatency - Return the latency value for this edge, which roughly
145 /// means the minimum number of cycles that must elapse between the
146 /// predecessor and the successor, given that they have this edge
148 unsigned getLatency() const {
152 /// setLatency - Set the latency for this edge.
153 void setLatency(unsigned Lat) {
157 /// getMinLatency - Return the minimum latency for this edge. Minimum
158 /// latency is used for scheduling groups, while normal (expected) latency
159 /// is for instruction cost and critical path.
160 unsigned getMinLatency() const {
164 /// setMinLatency - Set the minimum latency for this edge.
165 void setMinLatency(unsigned Lat) {
169 //// getSUnit - Return the SUnit to which this edge points.
170 SUnit *getSUnit() const {
171 return Dep.getPointer();
174 //// setSUnit - Assign the SUnit to which this edge points.
175 void setSUnit(SUnit *SU) {
179 /// getKind - Return an enum value representing the kind of the dependence.
180 Kind getKind() const {
184 /// isCtrl - Shorthand for getKind() != SDep::Data.
185 bool isCtrl() const {
186 return getKind() != Data;
189 /// isNormalMemory - Test if this is an Order dependence between two
190 /// memory accesses where both sides of the dependence access memory
191 /// in non-volatile and fully modeled ways.
192 bool isNormalMemory() const {
193 return getKind() == Order && (Contents.OrdKind == MayAliasMem
194 || Contents.OrdKind == MustAliasMem);
197 /// isMustAlias - Test if this is an Order dependence that is marked
198 /// as "must alias", meaning that the SUnits at either end of the edge
199 /// have a memory dependence on a known memory location.
200 bool isMustAlias() const {
201 return getKind() == Order && Contents.OrdKind == MustAliasMem;
204 /// isWeak - Test if this a weak dependence. Weak dependencies are
205 /// considered DAG edges for height computation and other heuristics, but do
206 /// not force ordering. Breaking a weak edge may require the scheduler to
207 /// compensate, for example by inserting a copy.
208 bool isWeak() const {
209 return getKind() == Order
210 && (Contents.OrdKind == Artificial || Contents.OrdKind == Cluster);
213 /// isArtificial - Test if this is an Order dependence that is marked
214 /// as "artificial", meaning it isn't necessary for correctness.
215 bool isArtificial() const {
216 return getKind() == Order && Contents.OrdKind == Artificial;
219 /// isCluster - Test if this is an Order dependence that is marked
220 /// as "cluster", meaning it is artificial and wants to be adjacent.
221 bool isCluster() const {
222 return getKind() == Order && Contents.OrdKind == Cluster;
225 /// isAssignedRegDep - Test if this is a Data dependence that is
226 /// associated with a register.
227 bool isAssignedRegDep() const {
228 return getKind() == Data && Contents.Reg != 0;
231 /// getReg - Return the register associated with this edge. This is
232 /// only valid on Data, Anti, and Output edges. On Data edges, this
233 /// value may be zero, meaning there is no associated register.
234 unsigned getReg() const {
235 assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
236 "getReg called on non-register dependence edge!");
240 /// setReg - Assign the associated register for this edge. This is
241 /// only valid on Data, Anti, and Output edges. On Anti and Output
242 /// edges, this value must not be zero. On Data edges, the value may
243 /// be zero, which would mean that no specific register is associated
245 void setReg(unsigned Reg) {
246 assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
247 "setReg called on non-register dependence edge!");
248 assert((getKind() != Anti || Reg != 0) &&
249 "SDep::Anti edge cannot use the zero register!");
250 assert((getKind() != Output || Reg != 0) &&
251 "SDep::Output edge cannot use the zero register!");
257 struct isPodLike<SDep> { static const bool value = true; };
259 /// SUnit - Scheduling unit. This is a node in the scheduling DAG.
262 SDNode *Node; // Representative node.
263 MachineInstr *Instr; // Alternatively, a MachineInstr.
265 SUnit *OrigNode; // If not this, the node from which
266 // this node was cloned.
267 // (SD scheduling only)
269 const MCSchedClassDesc *SchedClass; // NULL or resolved SchedClass.
271 // Preds/Succs - The SUnits before/after us in the graph.
272 SmallVector<SDep, 4> Preds; // All sunit predecessors.
273 SmallVector<SDep, 4> Succs; // All sunit successors.
275 typedef SmallVector<SDep, 4>::iterator pred_iterator;
276 typedef SmallVector<SDep, 4>::iterator succ_iterator;
277 typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator;
278 typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator;
280 unsigned NodeNum; // Entry # of node in the node vector.
281 unsigned NodeQueueId; // Queue id of node.
282 unsigned NumPreds; // # of SDep::Data preds.
283 unsigned NumSuccs; // # of SDep::Data sucss.
284 unsigned NumPredsLeft; // # of preds not scheduled.
285 unsigned NumSuccsLeft; // # of succs not scheduled.
286 unsigned WeakPredsLeft; // # of weak preds not scheduled.
287 unsigned WeakSuccsLeft; // # of weak succs not scheduled.
288 unsigned short NumRegDefsLeft; // # of reg defs with no scheduled use.
289 unsigned short Latency; // Node latency.
290 bool isVRegCycle : 1; // May use and def the same vreg.
291 bool isCall : 1; // Is a function call.
292 bool isCallOp : 1; // Is a function call operand.
293 bool isTwoAddress : 1; // Is a two-address instruction.
294 bool isCommutable : 1; // Is a commutable instruction.
295 bool hasPhysRegDefs : 1; // Has physreg defs that are being used.
296 bool hasPhysRegClobbers : 1; // Has any physreg defs, used or not.
297 bool isPending : 1; // True once pending.
298 bool isAvailable : 1; // True once available.
299 bool isScheduled : 1; // True once scheduled.
300 bool isScheduleHigh : 1; // True if preferable to schedule high.
301 bool isScheduleLow : 1; // True if preferable to schedule low.
302 bool isCloned : 1; // True if this node has been cloned.
303 Sched::Preference SchedulingPref; // Scheduling preference.
306 bool isDepthCurrent : 1; // True if Depth is current.
307 bool isHeightCurrent : 1; // True if Height is current.
308 unsigned Depth; // Node depth.
309 unsigned Height; // Node height.
311 unsigned TopReadyCycle; // Cycle relative to start when node is ready.
312 unsigned BotReadyCycle; // Cycle relative to end when node is ready.
314 const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null.
315 const TargetRegisterClass *CopySrcRC;
317 /// SUnit - Construct an SUnit for pre-regalloc scheduling to represent
318 /// an SDNode and any nodes flagged to it.
319 SUnit(SDNode *node, unsigned nodenum)
320 : Node(node), Instr(0), OrigNode(0), SchedClass(0), NodeNum(nodenum),
321 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
322 NumSuccsLeft(0), WeakPredsLeft(0), WeakSuccsLeft(0), NumRegDefsLeft(0),
323 Latency(0), isVRegCycle(false), isCall(false), isCallOp(false),
324 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
325 hasPhysRegClobbers(false), isPending(false), isAvailable(false),
326 isScheduled(false), isScheduleHigh(false), isScheduleLow(false),
327 isCloned(false), SchedulingPref(Sched::None),
328 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
329 TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {}
331 /// SUnit - Construct an SUnit for post-regalloc scheduling to represent
333 SUnit(MachineInstr *instr, unsigned nodenum)
334 : Node(0), Instr(instr), OrigNode(0), SchedClass(0), NodeNum(nodenum),
335 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
336 NumSuccsLeft(0), WeakPredsLeft(0), WeakSuccsLeft(0), NumRegDefsLeft(0),
337 Latency(0), isVRegCycle(false), isCall(false), isCallOp(false),
338 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
339 hasPhysRegClobbers(false), isPending(false), isAvailable(false),
340 isScheduled(false), isScheduleHigh(false), isScheduleLow(false),
341 isCloned(false), SchedulingPref(Sched::None),
342 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
343 TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {}
345 /// SUnit - Construct a placeholder SUnit.
347 : Node(0), Instr(0), OrigNode(0), SchedClass(0), NodeNum(~0u),
348 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
349 NumSuccsLeft(0), WeakPredsLeft(0), WeakSuccsLeft(0), NumRegDefsLeft(0),
350 Latency(0), isVRegCycle(false), isCall(false), isCallOp(false),
351 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
352 hasPhysRegClobbers(false), isPending(false), isAvailable(false),
353 isScheduled(false), isScheduleHigh(false), isScheduleLow(false),
354 isCloned(false), SchedulingPref(Sched::None),
355 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
356 TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {}
358 /// setNode - Assign the representative SDNode for this SUnit.
359 /// This may be used during pre-regalloc scheduling.
360 void setNode(SDNode *N) {
361 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!");
365 /// getNode - Return the representative SDNode for this SUnit.
366 /// This may be used during pre-regalloc scheduling.
367 SDNode *getNode() const {
368 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!");
372 /// isInstr - Return true if this SUnit refers to a machine instruction as
373 /// opposed to an SDNode.
374 bool isInstr() const { return Instr; }
376 /// setInstr - Assign the instruction for the SUnit.
377 /// This may be used during post-regalloc scheduling.
378 void setInstr(MachineInstr *MI) {
379 assert(!Node && "Setting MachineInstr of SUnit with SDNode!");
383 /// getInstr - Return the representative MachineInstr for this SUnit.
384 /// This may be used during post-regalloc scheduling.
385 MachineInstr *getInstr() const {
386 assert(!Node && "Reading MachineInstr of SUnit with SDNode!");
390 /// addPred - This adds the specified edge as a pred of the current node if
391 /// not already. It also adds the current node as a successor of the
393 bool addPred(const SDep &D, bool Required = true);
395 /// removePred - This removes the specified edge as a pred of the current
396 /// node if it exists. It also removes the current node as a successor of
397 /// the specified node.
398 void removePred(const SDep &D);
400 /// getDepth - Return the depth of this node, which is the length of the
401 /// maximum path up to any node which has no predecessors.
402 unsigned getDepth() const {
404 const_cast<SUnit *>(this)->ComputeDepth();
408 /// getHeight - Return the height of this node, which is the length of the
409 /// maximum path down to any node which has no successors.
410 unsigned getHeight() const {
411 if (!isHeightCurrent)
412 const_cast<SUnit *>(this)->ComputeHeight();
416 /// setDepthToAtLeast - If NewDepth is greater than this node's
417 /// depth value, set it to be the new depth value. This also
418 /// recursively marks successor nodes dirty.
419 void setDepthToAtLeast(unsigned NewDepth);
421 /// setDepthToAtLeast - If NewDepth is greater than this node's
422 /// depth value, set it to be the new height value. This also
423 /// recursively marks predecessor nodes dirty.
424 void setHeightToAtLeast(unsigned NewHeight);
426 /// setDepthDirty - Set a flag in this node to indicate that its
427 /// stored Depth value will require recomputation the next time
428 /// getDepth() is called.
429 void setDepthDirty();
431 /// setHeightDirty - Set a flag in this node to indicate that its
432 /// stored Height value will require recomputation the next time
433 /// getHeight() is called.
434 void setHeightDirty();
436 /// isPred - Test if node N is a predecessor of this node.
437 bool isPred(SUnit *N) {
438 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
439 if (Preds[i].getSUnit() == N)
444 /// isSucc - Test if node N is a successor of this node.
445 bool isSucc(SUnit *N) {
446 for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i)
447 if (Succs[i].getSUnit() == N)
452 bool isTopReady() const {
453 return NumPredsLeft == 0;
455 bool isBottomReady() const {
456 return NumSuccsLeft == 0;
459 void dump(const ScheduleDAG *G) const;
460 void dumpAll(const ScheduleDAG *G) const;
461 void print(raw_ostream &O, const ScheduleDAG *G) const;
465 void ComputeHeight();
468 //===--------------------------------------------------------------------===//
469 /// SchedulingPriorityQueue - This interface is used to plug different
470 /// priorities computation algorithms into the list scheduler. It implements
471 /// the interface of a standard priority queue, where nodes are inserted in
472 /// arbitrary order and returned in priority order. The computation of the
473 /// priority and the representation of the queue are totally up to the
474 /// implementation to decide.
476 class SchedulingPriorityQueue {
477 virtual void anchor();
481 SchedulingPriorityQueue(bool rf = false):
482 CurCycle(0), HasReadyFilter(rf) {}
483 virtual ~SchedulingPriorityQueue() {}
485 virtual bool isBottomUp() const = 0;
487 virtual void initNodes(std::vector<SUnit> &SUnits) = 0;
488 virtual void addNode(const SUnit *SU) = 0;
489 virtual void updateNode(const SUnit *SU) = 0;
490 virtual void releaseState() = 0;
492 virtual bool empty() const = 0;
494 bool hasReadyFilter() const { return HasReadyFilter; }
496 virtual bool tracksRegPressure() const { return false; }
498 virtual bool isReady(SUnit *) const {
499 assert(!HasReadyFilter && "The ready filter must override isReady()");
502 virtual void push(SUnit *U) = 0;
504 void push_all(const std::vector<SUnit *> &Nodes) {
505 for (std::vector<SUnit *>::const_iterator I = Nodes.begin(),
506 E = Nodes.end(); I != E; ++I)
510 virtual SUnit *pop() = 0;
512 virtual void remove(SUnit *SU) = 0;
514 virtual void dump(ScheduleDAG *) const {}
516 /// scheduledNode - As each node is scheduled, this method is invoked. This
517 /// allows the priority function to adjust the priority of related
518 /// unscheduled nodes, for example.
520 virtual void scheduledNode(SUnit *) {}
522 virtual void unscheduledNode(SUnit *) {}
524 void setCurCycle(unsigned Cycle) {
528 unsigned getCurCycle() const {
535 const TargetMachine &TM; // Target processor
536 const TargetInstrInfo *TII; // Target instruction information
537 const TargetRegisterInfo *TRI; // Target processor register info
538 MachineFunction &MF; // Machine function
539 MachineRegisterInfo &MRI; // Virtual/real register map
540 std::vector<SUnit> SUnits; // The scheduling units.
541 SUnit EntrySU; // Special node for the region entry.
542 SUnit ExitSU; // Special node for the region exit.
545 static const bool StressSched = false;
550 explicit ScheduleDAG(MachineFunction &mf);
552 virtual ~ScheduleDAG();
554 /// clearDAG - clear the DAG state (between regions).
557 /// getInstrDesc - Return the MCInstrDesc of this SUnit.
558 /// Return NULL for SDNodes without a machine opcode.
559 const MCInstrDesc *getInstrDesc(const SUnit *SU) const {
560 if (SU->isInstr()) return &SU->getInstr()->getDesc();
561 return getNodeDesc(SU->getNode());
564 /// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered
567 void viewGraph(const Twine &Name, const Twine &Title);
570 virtual void dumpNode(const SUnit *SU) const = 0;
572 /// getGraphNodeLabel - Return a label for an SUnit node in a visualization
573 /// of the ScheduleDAG.
574 virtual std::string getGraphNodeLabel(const SUnit *SU) const = 0;
576 /// getDAGLabel - Return a label for the region of code covered by the DAG.
577 virtual std::string getDAGName() const = 0;
579 /// addCustomGraphFeatures - Add custom features for a visualization of
581 virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {}
584 /// VerifyScheduledDAG - Verify that all SUnits were scheduled and that
585 /// their state is consistent. Return the number of scheduled SUnits.
586 unsigned VerifyScheduledDAG(bool isBottomUp);
590 // Return the MCInstrDesc of this SDNode or NULL.
591 const MCInstrDesc *getNodeDesc(const SDNode *Node) const;
594 class SUnitIterator : public std::iterator<std::forward_iterator_tag,
599 SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {}
601 bool operator==(const SUnitIterator& x) const {
602 return Operand == x.Operand;
604 bool operator!=(const SUnitIterator& x) const { return !operator==(x); }
606 const SUnitIterator &operator=(const SUnitIterator &I) {
607 assert(I.Node==Node && "Cannot assign iterators to two different nodes!");
612 pointer operator*() const {
613 return Node->Preds[Operand].getSUnit();
615 pointer operator->() const { return operator*(); }
617 SUnitIterator& operator++() { // Preincrement
621 SUnitIterator operator++(int) { // Postincrement
622 SUnitIterator tmp = *this; ++*this; return tmp;
625 static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); }
626 static SUnitIterator end (SUnit *N) {
627 return SUnitIterator(N, (unsigned)N->Preds.size());
630 unsigned getOperand() const { return Operand; }
631 const SUnit *getNode() const { return Node; }
632 /// isCtrlDep - Test if this is not an SDep::Data dependence.
633 bool isCtrlDep() const {
634 return getSDep().isCtrl();
636 bool isArtificialDep() const {
637 return getSDep().isArtificial();
639 const SDep &getSDep() const {
640 return Node->Preds[Operand];
644 template <> struct GraphTraits<SUnit*> {
645 typedef SUnit NodeType;
646 typedef SUnitIterator ChildIteratorType;
647 static inline NodeType *getEntryNode(SUnit *N) { return N; }
648 static inline ChildIteratorType child_begin(NodeType *N) {
649 return SUnitIterator::begin(N);
651 static inline ChildIteratorType child_end(NodeType *N) {
652 return SUnitIterator::end(N);
656 template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> {
657 typedef std::vector<SUnit>::iterator nodes_iterator;
658 static nodes_iterator nodes_begin(ScheduleDAG *G) {
659 return G->SUnits.begin();
661 static nodes_iterator nodes_end(ScheduleDAG *G) {
662 return G->SUnits.end();
666 /// ScheduleDAGTopologicalSort is a class that computes a topological
667 /// ordering for SUnits and provides methods for dynamically updating
668 /// the ordering as new edges are added.
670 /// This allows a very fast implementation of IsReachable, for example.
672 class ScheduleDAGTopologicalSort {
673 /// SUnits - A reference to the ScheduleDAG's SUnits.
674 std::vector<SUnit> &SUnits;
677 /// Index2Node - Maps topological index to the node number.
678 std::vector<int> Index2Node;
679 /// Node2Index - Maps the node number to its topological index.
680 std::vector<int> Node2Index;
681 /// Visited - a set of nodes visited during a DFS traversal.
684 /// DFS - make a DFS traversal and mark all nodes affected by the
685 /// edge insertion. These nodes will later get new topological indexes
686 /// by means of the Shift method.
687 void DFS(const SUnit *SU, int UpperBound, bool& HasLoop);
689 /// Shift - reassign topological indexes for the nodes in the DAG
690 /// to preserve the topological ordering.
691 void Shift(BitVector& Visited, int LowerBound, int UpperBound);
693 /// Allocate - assign the topological index to the node n.
694 void Allocate(int n, int index);
697 ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits, SUnit *ExitSU);
699 /// InitDAGTopologicalSorting - create the initial topological
700 /// ordering from the DAG to be scheduled.
701 void InitDAGTopologicalSorting();
703 /// IsReachable - Checks if SU is reachable from TargetSU.
704 bool IsReachable(const SUnit *SU, const SUnit *TargetSU);
706 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU
707 /// will create a cycle.
708 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU);
710 /// AddPred - Updates the topological ordering to accommodate an edge
711 /// to be added from SUnit X to SUnit Y.
712 void AddPred(SUnit *Y, SUnit *X);
714 /// RemovePred - Updates the topological ordering to accommodate an
715 /// an edge to be removed from the specified node N from the predecessors
716 /// of the current node M.
717 void RemovePred(SUnit *M, SUnit *N);
719 typedef std::vector<int>::iterator iterator;
720 typedef std::vector<int>::const_iterator const_iterator;
721 iterator begin() { return Index2Node.begin(); }
722 const_iterator begin() const { return Index2Node.begin(); }
723 iterator end() { return Index2Node.end(); }
724 const_iterator end() const { return Index2Node.end(); }
726 typedef std::vector<int>::reverse_iterator reverse_iterator;
727 typedef std::vector<int>::const_reverse_iterator const_reverse_iterator;
728 reverse_iterator rbegin() { return Index2Node.rbegin(); }
729 const_reverse_iterator rbegin() const { return Index2Node.rbegin(); }
730 reverse_iterator rend() { return Index2Node.rend(); }
731 const_reverse_iterator rend() const { return Index2Node.rend(); }