1 //===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAG class, which is used as the common
11 // base class for SelectionDAG-based instruction scheduler.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SCHEDULEDAG_H
16 #define LLVM_CODEGEN_SCHEDULEDAG_H
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/GraphTraits.h"
22 #include "llvm/ADT/SmallSet.h"
27 class MachineConstantPool;
28 class MachineFunction;
29 class MachineModuleInfo;
30 class MachineRegisterInfo;
32 class TargetRegisterInfo;
34 class SelectionDAGISel;
35 class TargetInstrInfo;
36 class TargetInstrDesc;
39 class TargetRegisterClass;
41 /// HazardRecognizer - This determines whether or not an instruction can be
42 /// issued this cycle, and whether or not a noop needs to be inserted to handle
44 class HazardRecognizer {
46 virtual ~HazardRecognizer();
49 NoHazard, // This instruction can be emitted at this cycle.
50 Hazard, // This instruction can't be emitted at this cycle.
51 NoopHazard // This instruction can't be emitted, and needs noops.
54 /// getHazardType - Return the hazard type of emitting this node. There are
55 /// three possible results. Either:
56 /// * NoHazard: it is legal to issue this instruction on this cycle.
57 /// * Hazard: issuing this instruction would stall the machine. If some
58 /// other instruction is available, issue it first.
59 /// * NoopHazard: issuing this instruction would break the program. If
60 /// some other instruction can be issued, do so, otherwise issue a noop.
61 virtual HazardType getHazardType(SDNode *) {
65 /// EmitInstruction - This callback is invoked when an instruction is
66 /// emitted, to advance the hazard state.
67 virtual void EmitInstruction(SDNode *) {}
69 /// AdvanceCycle - This callback is invoked when no instructions can be
70 /// issued on this cycle without a hazard. This should increment the
71 /// internal state of the hazard recognizer so that previously "Hazard"
72 /// instructions will now not be hazards.
73 virtual void AdvanceCycle() {}
75 /// EmitNoop - This callback is invoked when a noop was added to the
76 /// instruction stream.
77 virtual void EmitNoop() {}
80 /// SDep - Scheduling dependency. It keeps track of dependent nodes,
81 /// cost of the depdenency, etc.
83 SUnit *Dep; // Dependent - either a predecessor or a successor.
84 unsigned Reg; // If non-zero, this dep is a phy register dependency.
85 int Cost; // Cost of the dependency.
86 bool isCtrl : 1; // True iff it's a control dependency.
87 bool isSpecial : 1; // True iff it's a special ctrl dep added during sched.
88 SDep(SUnit *d, unsigned r, int t, bool c, bool s)
89 : Dep(d), Reg(r), Cost(t), isCtrl(c), isSpecial(s) {}
92 /// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
93 /// a group of nodes flagged together.
96 SDNode *Node; // Representative node.
98 SUnit *OrigNode; // If not this, the node from which
99 // this node was cloned.
101 // Preds/Succs - The SUnits before/after us in the graph. The boolean value
102 // is true if the edge is a token chain edge, false if it is a value edge.
103 SmallVector<SDep, 4> Preds; // All sunit predecessors.
104 SmallVector<SDep, 4> Succs; // All sunit successors.
106 typedef SmallVector<SDep, 4>::iterator pred_iterator;
107 typedef SmallVector<SDep, 4>::iterator succ_iterator;
108 typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator;
109 typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator;
111 unsigned NodeNum; // Entry # of node in the node vector.
112 unsigned NodeQueueId; // Queue id of node.
113 unsigned short Latency; // Node latency.
114 short NumPreds; // # of preds.
115 short NumSuccs; // # of sucss.
116 short NumPredsLeft; // # of preds not scheduled.
117 short NumSuccsLeft; // # of succs not scheduled.
118 bool isTwoAddress : 1; // Is a two-address instruction.
119 bool isCommutable : 1; // Is a commutable instruction.
120 bool hasPhysRegDefs : 1; // Has physreg defs that are being used.
121 bool isPending : 1; // True once pending.
122 bool isAvailable : 1; // True once available.
123 bool isScheduled : 1; // True once scheduled.
124 unsigned CycleBound; // Upper/lower cycle to be scheduled at.
125 unsigned Cycle; // Once scheduled, the cycle of the op.
126 unsigned Depth; // Node depth;
127 unsigned Height; // Node height;
128 const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null.
129 const TargetRegisterClass *CopySrcRC;
131 SUnit(SDNode *node, unsigned nodenum)
132 : Node(node), OrigNode(0), NodeNum(nodenum), NodeQueueId(0), Latency(0),
133 NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
134 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
135 isPending(false), isAvailable(false), isScheduled(false),
136 CycleBound(0), Cycle(0), Depth(0), Height(0),
137 CopyDstRC(NULL), CopySrcRC(NULL) {}
139 /// setNode - Assign the representative SDNode for this SUnit.
140 void setNode(SDNode *N) { Node = N; }
142 /// getNode - Return the representative SDNode for this SUnit.
143 SDNode *getNode() const { return Node; }
145 /// addPred - This adds the specified node as a pred of the current node if
146 /// not already. This returns true if this is a new pred.
147 bool addPred(SUnit *N, bool isCtrl, bool isSpecial,
148 unsigned PhyReg = 0, int Cost = 1) {
149 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
150 if (Preds[i].Dep == N &&
151 Preds[i].isCtrl == isCtrl && Preds[i].isSpecial == isSpecial)
153 Preds.push_back(SDep(N, PhyReg, Cost, isCtrl, isSpecial));
154 N->Succs.push_back(SDep(this, PhyReg, Cost, isCtrl, isSpecial));
166 bool removePred(SUnit *N, bool isCtrl, bool isSpecial) {
167 for (SmallVector<SDep, 4>::iterator I = Preds.begin(), E = Preds.end();
169 if (I->Dep == N && I->isCtrl == isCtrl && I->isSpecial == isSpecial) {
170 bool FoundSucc = false;
171 for (SmallVector<SDep, 4>::iterator II = N->Succs.begin(),
172 EE = N->Succs.end(); II != EE; ++II)
173 if (II->Dep == this &&
174 II->isCtrl == isCtrl && II->isSpecial == isSpecial) {
179 assert(FoundSucc && "Mismatching preds / succs lists!");
194 bool isPred(SUnit *N) {
195 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
196 if (Preds[i].Dep == N)
201 bool isSucc(SUnit *N) {
202 for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i)
203 if (Succs[i].Dep == N)
208 void dump(const SelectionDAG *G) const;
209 void dumpAll(const SelectionDAG *G) const;
212 //===--------------------------------------------------------------------===//
213 /// SchedulingPriorityQueue - This interface is used to plug different
214 /// priorities computation algorithms into the list scheduler. It implements
215 /// the interface of a standard priority queue, where nodes are inserted in
216 /// arbitrary order and returned in priority order. The computation of the
217 /// priority and the representation of the queue are totally up to the
218 /// implementation to decide.
220 class SchedulingPriorityQueue {
222 virtual ~SchedulingPriorityQueue() {}
224 virtual void initNodes(std::vector<SUnit> &SUnits) = 0;
225 virtual void addNode(const SUnit *SU) = 0;
226 virtual void updateNode(const SUnit *SU) = 0;
227 virtual void releaseState() = 0;
229 virtual unsigned size() const = 0;
230 virtual bool empty() const = 0;
231 virtual void push(SUnit *U) = 0;
233 virtual void push_all(const std::vector<SUnit *> &Nodes) = 0;
234 virtual SUnit *pop() = 0;
236 virtual void remove(SUnit *SU) = 0;
238 /// ScheduledNode - As each node is scheduled, this method is invoked. This
239 /// allows the priority function to adjust the priority of related
240 /// unscheduled nodes, for example.
242 virtual void ScheduledNode(SUnit *) {}
244 virtual void UnscheduledNode(SUnit *) {}
249 SelectionDAG *DAG; // DAG of the current basic block
250 MachineBasicBlock *BB; // Current basic block
251 const TargetMachine &TM; // Target processor
252 const TargetInstrInfo *TII; // Target instruction information
253 const TargetRegisterInfo *TRI; // Target processor register info
254 TargetLowering *TLI; // Target lowering info
255 MachineFunction *MF; // Machine function
256 MachineRegisterInfo &MRI; // Virtual/real register map
257 MachineConstantPool *ConstPool; // Target constant pool
258 std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s
259 // represent noop instructions.
260 std::vector<SUnit> SUnits; // The scheduling units.
261 SmallSet<SDNode*, 16> CommuteSet; // Nodes that should be commuted.
263 ScheduleDAG(SelectionDAG *dag, MachineBasicBlock *bb,
264 const TargetMachine &tm);
266 virtual ~ScheduleDAG() {}
268 /// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered
273 /// Run - perform scheduling.
277 /// isPassiveNode - Return true if the node is a non-scheduled leaf.
279 static bool isPassiveNode(SDNode *Node) {
280 if (isa<ConstantSDNode>(Node)) return true;
281 if (isa<ConstantFPSDNode>(Node)) return true;
282 if (isa<RegisterSDNode>(Node)) return true;
283 if (isa<GlobalAddressSDNode>(Node)) return true;
284 if (isa<BasicBlockSDNode>(Node)) return true;
285 if (isa<FrameIndexSDNode>(Node)) return true;
286 if (isa<ConstantPoolSDNode>(Node)) return true;
287 if (isa<JumpTableSDNode>(Node)) return true;
288 if (isa<ExternalSymbolSDNode>(Node)) return true;
289 if (isa<MemOperandSDNode>(Node)) return true;
290 if (Node->getOpcode() == ISD::EntryToken) return true;
294 /// NewSUnit - Creates a new SUnit and return a ptr to it.
296 SUnit *NewSUnit(SDNode *N) {
297 SUnits.push_back(SUnit(N, (unsigned)SUnits.size()));
298 SUnits.back().OrigNode = &SUnits.back();
299 return &SUnits.back();
302 /// Clone - Creates a clone of the specified SUnit. It does not copy the
303 /// predecessors / successors info nor the temporary scheduling states.
304 SUnit *Clone(SUnit *N);
306 /// BuildSchedUnits - Build SUnits from the selection dag that we are input.
307 /// This SUnit graph is similar to the SelectionDAG, but represents flagged
308 /// together nodes with a single SUnit.
309 void BuildSchedUnits();
311 /// ComputeLatency - Compute node latency.
313 void ComputeLatency(SUnit *SU);
315 /// CalculateDepths, CalculateHeights - Calculate node depth / height.
317 void CalculateDepths();
318 void CalculateHeights();
320 /// CountResults - The results of target nodes have register or immediate
321 /// operands first, then an optional chain, and optional flag operands
322 /// (which do not go into the machine instrs.)
323 static unsigned CountResults(SDNode *Node);
325 /// CountOperands - The inputs to target nodes have any actual inputs first,
326 /// followed by special operands that describe memory references, then an
327 /// optional chain operand, then flag operands. Compute the number of
328 /// actual operands that will go into the resulting MachineInstr.
329 static unsigned CountOperands(SDNode *Node);
331 /// ComputeMemOperandsEnd - Find the index one past the last
332 /// MemOperandSDNode operand
333 static unsigned ComputeMemOperandsEnd(SDNode *Node);
335 /// EmitNode - Generate machine code for an node and needed dependencies.
336 /// VRBaseMap contains, for each already emitted node, the first virtual
337 /// register number for the results of the node.
339 void EmitNode(SDNode *Node, bool IsClone,
340 DenseMap<SDValue, unsigned> &VRBaseMap);
342 /// EmitNoop - Emit a noop instruction.
346 MachineBasicBlock *EmitSchedule();
348 void dumpSchedule() const;
350 /// Schedule - Order nodes according to selected style, filling
351 /// in the Sequence member.
353 virtual void Schedule() = 0;
356 /// EmitSubregNode - Generate machine code for subreg nodes.
358 void EmitSubregNode(SDNode *Node,
359 DenseMap<SDValue, unsigned> &VRBaseMap);
361 /// getVR - Return the virtual register corresponding to the specified result
362 /// of the specified node.
363 unsigned getVR(SDValue Op, DenseMap<SDValue, unsigned> &VRBaseMap);
365 /// getDstOfCopyToRegUse - If the only use of the specified result number of
366 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
367 unsigned getDstOfOnlyCopyToRegUse(SDNode *Node, unsigned ResNo) const;
369 void AddOperand(MachineInstr *MI, SDValue Op, unsigned IIOpNum,
370 const TargetInstrDesc *II,
371 DenseMap<SDValue, unsigned> &VRBaseMap);
372 void AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO);
374 void EmitCrossRCCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap);
376 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
377 /// implicit physical register output.
378 void EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
380 DenseMap<SDValue, unsigned> &VRBaseMap);
382 void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
383 const TargetInstrDesc &II,
384 DenseMap<SDValue, unsigned> &VRBaseMap);
386 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
387 /// physical register has only a single copy use, then coalesced the copy
389 void EmitLiveInCopy(MachineBasicBlock *MBB,
390 MachineBasicBlock::iterator &InsertPos,
391 unsigned VirtReg, unsigned PhysReg,
392 const TargetRegisterClass *RC,
393 DenseMap<MachineInstr*, unsigned> &CopyRegMap);
395 /// EmitLiveInCopies - If this is the first basic block in the function,
396 /// and if it has live ins that need to be copied into vregs, emit the
397 /// copies into the top of the block.
398 void EmitLiveInCopies(MachineBasicBlock *MBB);
401 /// createBURRListDAGScheduler - This creates a bottom up register usage
402 /// reduction list scheduler.
403 ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS,
405 const TargetMachine *TM,
406 MachineBasicBlock *BB,
409 /// createTDRRListDAGScheduler - This creates a top down register usage
410 /// reduction list scheduler.
411 ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS,
413 const TargetMachine *TM,
414 MachineBasicBlock *BB,
417 /// createTDListDAGScheduler - This creates a top-down list scheduler with
418 /// a hazard recognizer.
419 ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS,
421 const TargetMachine *TM,
422 MachineBasicBlock *BB,
425 /// createFastDAGScheduler - This creates a "fast" scheduler.
427 ScheduleDAG *createFastDAGScheduler(SelectionDAGISel *IS,
429 const TargetMachine *TM,
430 MachineBasicBlock *BB,
433 /// createDefaultScheduler - This creates an instruction scheduler appropriate
435 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
437 const TargetMachine *TM,
438 MachineBasicBlock *BB,
441 class SUnitIterator : public forward_iterator<SUnit, ptrdiff_t> {
445 SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {}
447 bool operator==(const SUnitIterator& x) const {
448 return Operand == x.Operand;
450 bool operator!=(const SUnitIterator& x) const { return !operator==(x); }
452 const SUnitIterator &operator=(const SUnitIterator &I) {
453 assert(I.Node == Node && "Cannot assign iterators to two different nodes!");
458 pointer operator*() const {
459 return Node->Preds[Operand].Dep;
461 pointer operator->() const { return operator*(); }
463 SUnitIterator& operator++() { // Preincrement
467 SUnitIterator operator++(int) { // Postincrement
468 SUnitIterator tmp = *this; ++*this; return tmp;
471 static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); }
472 static SUnitIterator end (SUnit *N) {
473 return SUnitIterator(N, (unsigned)N->Preds.size());
476 unsigned getOperand() const { return Operand; }
477 const SUnit *getNode() const { return Node; }
478 bool isCtrlDep() const { return Node->Preds[Operand].isCtrl; }
479 bool isSpecialDep() const { return Node->Preds[Operand].isSpecial; }
482 template <> struct GraphTraits<SUnit*> {
483 typedef SUnit NodeType;
484 typedef SUnitIterator ChildIteratorType;
485 static inline NodeType *getEntryNode(SUnit *N) { return N; }
486 static inline ChildIteratorType child_begin(NodeType *N) {
487 return SUnitIterator::begin(N);
489 static inline ChildIteratorType child_end(NodeType *N) {
490 return SUnitIterator::end(N);
494 template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> {
495 typedef std::vector<SUnit>::iterator nodes_iterator;
496 static nodes_iterator nodes_begin(ScheduleDAG *G) {
497 return G->SUnits.begin();
499 static nodes_iterator nodes_end(ScheduleDAG *G) {
500 return G->SUnits.end();