1 //===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAG class, which is used as the common
11 // base class for SelectionDAG-based instruction scheduler.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SCHEDULEDAG_H
16 #define LLVM_CODEGEN_SCHEDULEDAG_H
18 #include "llvm/CodeGen/SelectionDAG.h"
22 class MachineConstantPool;
23 class MachineDebugInfo;
28 class TargetInstrInfo;
29 class TargetInstrDescriptor;
33 typedef NodeInfo *NodeInfoPtr;
34 typedef std::vector<NodeInfoPtr> NIVector;
35 typedef std::vector<NodeInfoPtr>::iterator NIIterator;
38 // Scheduling heuristics
39 enum SchedHeuristics {
40 noScheduling, // No scheduling, emit breath first sequence.
41 simpleScheduling, // Two pass, min. critical path, max. utilization.
42 simpleNoItinScheduling, // Same as above exact using generic latency.
43 listSchedulingBURR, // Bottom up reg reduction list scheduling.
47 //===--------------------------------------------------------------------===//
49 /// Node group - This struct is used to manage flagged node groups.
53 NIVector Members; // Group member nodes
54 NodeInfo *Dominator; // Node with highest latency
55 unsigned Latency; // Total latency of the group
56 int Pending; // Number of visits pending before
61 NodeGroup() : Dominator(NULL), Pending(0) {}
64 inline void setDominator(NodeInfo *D) { Dominator = D; }
65 inline NodeInfo *getDominator() { return Dominator; }
66 inline void setLatency(unsigned L) { Latency = L; }
67 inline unsigned getLatency() { return Latency; }
68 inline int getPending() const { return Pending; }
69 inline void setPending(int P) { Pending = P; }
70 inline int addPending(int I) { return Pending += I; }
73 inline bool group_empty() { return Members.empty(); }
74 inline NIIterator group_begin() { return Members.begin(); }
75 inline NIIterator group_end() { return Members.end(); }
76 inline void group_push_back(const NodeInfoPtr &NI) {
77 Members.push_back(NI);
79 inline NIIterator group_insert(NIIterator Pos, const NodeInfoPtr &NI) {
80 return Members.insert(Pos, NI);
82 inline void group_insert(NIIterator Pos, NIIterator First,
84 Members.insert(Pos, First, Last);
87 static void Add(NodeInfo *D, NodeInfo *U);
90 //===--------------------------------------------------------------------===//
92 /// NodeInfo - This struct tracks information used to schedule the a node.
96 int Pending; // Number of visits pending before
99 SDNode *Node; // DAG node
100 InstrStage *StageBegin; // First stage in itinerary
101 InstrStage *StageEnd; // Last+1 stage in itinerary
102 unsigned Latency; // Total cycles to complete instr
103 bool IsCall : 1; // Is function call
104 bool IsLoad : 1; // Is memory load
105 bool IsStore : 1; // Is memory store
106 unsigned Slot; // Node's time slot
107 NodeGroup *Group; // Grouping information
108 unsigned VRBase; // Virtual register base
110 unsigned Preorder; // Index before scheduling
114 NodeInfo(SDNode *N = NULL)
130 inline bool isInGroup() const {
131 assert(!Group || !Group->group_empty() && "Group with no members");
132 return Group != NULL;
134 inline bool isGroupDominator() const {
135 return isInGroup() && Group->getDominator() == this;
137 inline int getPending() const {
138 return Group ? Group->getPending() : Pending;
140 inline void setPending(int P) {
141 if (Group) Group->setPending(P);
144 inline int addPending(int I) {
145 if (Group) return Group->addPending(I);
146 else return Pending += I;
150 //===--------------------------------------------------------------------===//
152 /// NodeGroupIterator - Iterates over all the nodes indicated by the node
153 /// info. If the node is in a group then iterate over the members of the
154 /// group, otherwise just the node info.
156 class NodeGroupIterator {
158 NodeInfo *NI; // Node info
159 NIIterator NGI; // Node group iterator
160 NIIterator NGE; // Node group iterator end
164 NodeGroupIterator(NodeInfo *N) : NI(N) {
165 // If the node is in a group then set up the group iterator. Otherwise
166 // the group iterators will trip first time out.
167 if (N->isInGroup()) {
169 NodeGroup *Group = NI->Group;
170 NGI = Group->group_begin();
171 NGE = Group->group_end();
172 // Prevent this node from being used (will be in members list
177 /// next - Return the next node info, otherwise NULL.
181 if (NGI != NGE) return *NGI++;
182 // Use node as the result (may be NULL)
183 NodeInfo *Result = NI;
186 // Return node or NULL
190 //===--------------------------------------------------------------------===//
193 //===--------------------------------------------------------------------===//
195 /// NodeGroupOpIterator - Iterates over all the operands of a node. If the
196 /// node is a member of a group, this iterates over all the operands of all
197 /// the members of the group.
199 class NodeGroupOpIterator {
201 NodeInfo *NI; // Node containing operands
202 NodeGroupIterator GI; // Node group iterator
203 SDNode::op_iterator OI; // Operand iterator
204 SDNode::op_iterator OE; // Operand iterator end
206 /// CheckNode - Test if node has more operands. If not get the next node
207 /// skipping over nodes that have no operands.
209 // Only if operands are exhausted first
211 // Get next node info
212 NodeInfo *NI = GI.next();
213 // Exit if nodes are exhausted
216 SDNode *Node = NI->Node;
217 // Set up the operand iterators
218 OI = Node->op_begin();
225 NodeGroupOpIterator(NodeInfo *N)
226 : NI(N), GI(N), OI(SDNode::op_iterator()), OE(SDNode::op_iterator()) {}
228 /// isEnd - Returns true when not more operands are available.
230 inline bool isEnd() { CheckNode(); return OI == OE; }
232 /// next - Returns the next available operand.
234 inline SDOperand next() {
236 "Not checking for end of NodeGroupOpIterator correctly");
243 SchedHeuristics Heuristic; // Scheduling heuristic
244 SelectionDAG &DAG; // DAG of the current basic block
245 MachineBasicBlock *BB; // Current basic block
246 const TargetMachine &TM; // Target processor
247 const TargetInstrInfo *TII; // Target instruction information
248 const MRegisterInfo *MRI; // Target processor register info
249 SSARegMap *RegMap; // Virtual/real register map
250 MachineConstantPool *ConstPool; // Target constant pool
251 std::map<SDNode *, NodeInfo *> Map; // Map nodes to info
252 unsigned NodeCount; // Number of nodes in DAG
253 bool HasGroups; // True if there are any groups
254 NodeInfo *Info; // Info for nodes being scheduled
255 NIVector Ordering; // Emit ordering of nodes
257 ScheduleDAG(SchedHeuristics hstc, SelectionDAG &dag, MachineBasicBlock *bb,
258 const TargetMachine &tm)
259 : Heuristic(hstc), DAG(dag), BB(bb), TM(tm),
260 NodeCount(0), HasGroups(false), Info(NULL) {}
262 virtual ~ScheduleDAG() {};
264 /// Run - perform scheduling.
266 MachineBasicBlock *Run();
268 /// getNI - Returns the node info for the specified node.
270 NodeInfo *getNI(SDNode *Node) { return Map[Node]; }
272 /// getVR - Returns the virtual register number of the node.
274 unsigned getVR(SDOperand Op) {
275 NodeInfo *NI = getNI(Op.Val);
276 assert(NI->VRBase != 0 && "Node emitted out of order - late");
277 return NI->VRBase + Op.ResNo;
280 /// isPassiveNode - Return true if the node is a non-scheduled leaf.
282 bool isPassiveNode(SDNode *Node) {
283 if (isa<ConstantSDNode>(Node)) return true;
284 if (isa<RegisterSDNode>(Node)) return true;
285 if (isa<GlobalAddressSDNode>(Node)) return true;
286 if (isa<BasicBlockSDNode>(Node)) return true;
287 if (isa<FrameIndexSDNode>(Node)) return true;
288 if (isa<ConstantPoolSDNode>(Node)) return true;
289 if (isa<ExternalSymbolSDNode>(Node)) return true;
293 /// EmitNode - Generate machine code for an node and needed dependencies.
295 void EmitNode(NodeInfo *NI);
297 /// EmitAll - Emit all nodes in schedule sorted order.
301 /// Schedule - Order nodes according to selected style.
303 virtual void Schedule() {};
305 /// printNI - Print node info.
307 void printNI(std::ostream &O, NodeInfo *NI) const;
309 /// printChanges - Hilight changes in order caused by scheduling.
311 void printChanges(unsigned Index) const;
313 /// print - Print ordering to specified output stream.
315 void print(std::ostream &O) const;
317 void dump(const char *tag) const;
322 /// PrepareNodeInfo - Set up the basic minimum node info for scheduling.
324 void PrepareNodeInfo();
326 /// IdentifyGroups - Put flagged nodes into groups.
328 void IdentifyGroups();
331 /// createSimpleDAGScheduler - This creates a simple two pass instruction
333 ScheduleDAG* createSimpleDAGScheduler(SchedHeuristics Heuristic,
335 MachineBasicBlock *BB);
337 /// createBURRListDAGScheduler - This creates a bottom up register usage
338 /// reduction list scheduler.
339 ScheduleDAG* createBURRListDAGScheduler(SelectionDAG &DAG,
340 MachineBasicBlock *BB);