1 //===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAG class, which is used as the common
11 // base class for instruction schedulers.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SCHEDULEDAG_H
16 #define LLVM_CODEGEN_SCHEDULEDAG_H
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/GraphTraits.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/PointerIntPair.h"
28 class MachineConstantPool;
29 class MachineFunction;
30 class MachineModuleInfo;
31 class MachineRegisterInfo;
33 class TargetRegisterInfo;
36 class TargetInstrInfo;
37 class TargetInstrDesc;
40 class TargetRegisterClass;
41 template<class Graph> class GraphWriter;
43 /// SDep - Scheduling dependency. This represents one direction of an
44 /// edge in the scheduling DAG.
47 /// Kind - These are the different kinds of scheduling dependencies.
49 Data, ///< Regular data dependence (aka true-dependence).
50 Anti, ///< A register anti-dependedence (aka WAR).
51 Output, ///< A register output-dependence (aka WAW).
52 Order ///< Any other ordering dependency.
56 /// Dep - A pointer to the depending/depended-on SUnit, and an enum
57 /// indicating the kind of the dependency.
58 PointerIntPair<SUnit *, 2, Kind> Dep;
60 /// Contents - A union discriminated by the dependence kind.
62 /// Reg - For Data, Anti, and Output dependencies, the associated
63 /// register. For Data dependencies that don't currently have a register
64 /// assigned, this is set to zero.
67 /// Order - Additional information about Order dependencies.
69 /// isNormalMemory - True if both sides of the dependence
70 /// access memory in non-volatile and fully modeled ways.
71 bool isNormalMemory : 1;
73 /// isMustAlias - True if both sides of the dependence are known to
74 /// access the same memory.
77 /// isArtificial - True if this is an artificial dependency, meaning
78 /// it is not necessary for program correctness, and may be safely
79 /// deleted if necessary.
80 bool isArtificial : 1;
84 /// Latency - The time associated with this edge. Often this is just
85 /// the value of the Latency field of the predecessor, however advanced
86 /// models may provide additional information about specific edges.
90 /// SDep - Construct a null SDep. This is only for use by container
91 /// classes which require default constructors. SUnits may not
92 /// have null SDep edges.
93 SDep() : Dep(0, Data) {}
95 /// SDep - Construct an SDep with the specified values.
96 SDep(SUnit *S, Kind kind, unsigned latency = 1, unsigned Reg = 0,
97 bool isNormalMemory = false, bool isMustAlias = false,
98 bool isArtificial = false)
99 : Dep(S, kind), Contents(), Latency(latency) {
104 "SDep::Anti and SDep::Output must use a non-zero Reg!");
107 assert(!isMustAlias && "isMustAlias only applies with SDep::Order!");
108 assert(!isArtificial && "isArtificial only applies with SDep::Order!");
112 assert(Reg == 0 && "Reg given for non-register dependence!");
113 Contents.Order.isNormalMemory = isNormalMemory;
114 Contents.Order.isMustAlias = isMustAlias;
115 Contents.Order.isArtificial = isArtificial;
120 bool operator==(const SDep &Other) const {
121 if (Dep != Other.Dep || Latency != Other.Latency) return false;
122 switch (Dep.getInt()) {
126 return Contents.Reg == Other.Contents.Reg;
128 return Contents.Order.isNormalMemory ==
129 Other.Contents.Order.isNormalMemory &&
130 Contents.Order.isMustAlias == Other.Contents.Order.isMustAlias &&
131 Contents.Order.isArtificial == Other.Contents.Order.isArtificial;
133 assert(0 && "Invalid dependency kind!");
137 bool operator!=(const SDep &Other) const {
138 return !operator==(Other);
141 /// getLatency - Return the latency value for this edge, which roughly
142 /// means the minimum number of cycles that must elapse between the
143 /// predecessor and the successor, given that they have this edge
145 unsigned getLatency() const {
149 /// setLatency - Set the latency for this edge.
150 void setLatency(unsigned Lat) {
154 //// getSUnit - Return the SUnit to which this edge points.
155 SUnit *getSUnit() const {
156 return Dep.getPointer();
159 //// setSUnit - Assign the SUnit to which this edge points.
160 void setSUnit(SUnit *SU) {
164 /// getKind - Return an enum value representing the kind of the dependence.
165 Kind getKind() const {
169 /// isCtrl - Shorthand for getKind() != SDep::Data.
170 bool isCtrl() const {
171 return getKind() != Data;
174 /// isNormalMemory - Test if this is an Order dependence between two
175 /// memory accesses where both sides of the dependence access memory
176 /// in non-volatile and fully modeled ways.
177 bool isNormalMemory() const {
178 return getKind() == Order && Contents.Order.isNormalMemory;
181 /// isMustAlias - Test if this is an Order dependence that is marked
182 /// as "must alias", meaning that the SUnits at either end of the edge
183 /// have a memory dependence on a known memory location.
184 bool isMustAlias() const {
185 return getKind() == Order && Contents.Order.isMustAlias;
188 /// isArtificial - Test if this is an Order dependence that is marked
189 /// as "artificial", meaning it isn't necessary for correctness.
190 bool isArtificial() const {
191 return getKind() == Order && Contents.Order.isArtificial;
194 /// isAssignedRegDep - Test if this is a Data dependence that is
195 /// associated with a register.
196 bool isAssignedRegDep() const {
197 return getKind() == Data && Contents.Reg != 0;
200 /// getReg - Return the register associated with this edge. This is
201 /// only valid on Data, Anti, and Output edges. On Data edges, this
202 /// value may be zero, meaning there is no associated register.
203 unsigned getReg() const {
204 assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
205 "getReg called on non-register dependence edge!");
209 /// setReg - Assign the associated register for this edge. This is
210 /// only valid on Data, Anti, and Output edges. On Anti and Output
211 /// edges, this value must not be zero. On Data edges, the value may
212 /// be zero, which would mean that no specific register is associated
214 void setReg(unsigned Reg) {
215 assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
216 "setReg called on non-register dependence edge!");
217 assert((getKind() != Anti || Reg != 0) &&
218 "SDep::Anti edge cannot use the zero register!");
219 assert((getKind() != Output || Reg != 0) &&
220 "SDep::Output edge cannot use the zero register!");
225 /// SUnit - Scheduling unit. This is a node in the scheduling DAG.
228 SDNode *Node; // Representative node.
229 MachineInstr *Instr; // Alternatively, a MachineInstr.
231 SUnit *OrigNode; // If not this, the node from which
232 // this node was cloned.
234 // Preds/Succs - The SUnits before/after us in the graph. The boolean value
235 // is true if the edge is a token chain edge, false if it is a value edge.
236 SmallVector<SDep, 4> Preds; // All sunit predecessors.
237 SmallVector<SDep, 4> Succs; // All sunit successors.
239 typedef SmallVector<SDep, 4>::iterator pred_iterator;
240 typedef SmallVector<SDep, 4>::iterator succ_iterator;
241 typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator;
242 typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator;
244 unsigned NodeNum; // Entry # of node in the node vector.
245 unsigned NodeQueueId; // Queue id of node.
246 unsigned short Latency; // Node latency.
247 unsigned NumPreds; // # of SDep::Data preds.
248 unsigned NumSuccs; // # of SDep::Data sucss.
249 unsigned NumPredsLeft; // # of preds not scheduled.
250 unsigned NumSuccsLeft; // # of succs not scheduled.
251 bool isTwoAddress : 1; // Is a two-address instruction.
252 bool isCommutable : 1; // Is a commutable instruction.
253 bool hasPhysRegDefs : 1; // Has physreg defs that are being used.
254 bool hasPhysRegClobbers : 1; // Has any physreg defs, used or not.
255 bool isPending : 1; // True once pending.
256 bool isAvailable : 1; // True once available.
257 bool isScheduled : 1; // True once scheduled.
258 bool isScheduleHigh : 1; // True if preferable to schedule high.
259 bool isCloned : 1; // True if this node has been cloned.
261 bool isDepthCurrent : 1; // True if Depth is current.
262 bool isHeightCurrent : 1; // True if Height is current.
263 unsigned Depth; // Node depth.
264 unsigned Height; // Node height.
266 const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null.
267 const TargetRegisterClass *CopySrcRC;
269 /// SUnit - Construct an SUnit for pre-regalloc scheduling to represent
270 /// an SDNode and any nodes flagged to it.
271 SUnit(SDNode *node, unsigned nodenum)
272 : Node(node), Instr(0), OrigNode(0), NodeNum(nodenum), NodeQueueId(0),
273 Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
274 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
275 hasPhysRegClobbers(false),
276 isPending(false), isAvailable(false), isScheduled(false),
277 isScheduleHigh(false), isCloned(false),
278 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
279 CopyDstRC(NULL), CopySrcRC(NULL) {}
281 /// SUnit - Construct an SUnit for post-regalloc scheduling to represent
283 SUnit(MachineInstr *instr, unsigned nodenum)
284 : Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum), NodeQueueId(0),
285 Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
286 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
287 hasPhysRegClobbers(false),
288 isPending(false), isAvailable(false), isScheduled(false),
289 isScheduleHigh(false), isCloned(false),
290 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
291 CopyDstRC(NULL), CopySrcRC(NULL) {}
293 /// SUnit - Construct a placeholder SUnit.
295 : Node(0), Instr(0), OrigNode(0), NodeNum(~0u), NodeQueueId(0),
296 Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
297 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
298 hasPhysRegClobbers(false),
299 isPending(false), isAvailable(false), isScheduled(false),
300 isScheduleHigh(false), isCloned(false),
301 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
302 CopyDstRC(NULL), CopySrcRC(NULL) {}
304 /// setNode - Assign the representative SDNode for this SUnit.
305 /// This may be used during pre-regalloc scheduling.
306 void setNode(SDNode *N) {
307 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!");
311 /// getNode - Return the representative SDNode for this SUnit.
312 /// This may be used during pre-regalloc scheduling.
313 SDNode *getNode() const {
314 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!");
318 /// setInstr - Assign the instruction for the SUnit.
319 /// This may be used during post-regalloc scheduling.
320 void setInstr(MachineInstr *MI) {
321 assert(!Node && "Setting MachineInstr of SUnit with SDNode!");
325 /// getInstr - Return the representative MachineInstr for this SUnit.
326 /// This may be used during post-regalloc scheduling.
327 MachineInstr *getInstr() const {
328 assert(!Node && "Reading MachineInstr of SUnit with SDNode!");
332 /// addPred - This adds the specified edge as a pred of the current node if
333 /// not already. It also adds the current node as a successor of the
335 void addPred(const SDep &D);
337 /// removePred - This removes the specified edge as a pred of the current
338 /// node if it exists. It also removes the current node as a successor of
339 /// the specified node.
340 void removePred(const SDep &D);
342 /// getDepth - Return the depth of this node, which is the length of the
343 /// maximum path up to any node with has no predecessors.
344 unsigned getDepth() const {
345 if (!isDepthCurrent) const_cast<SUnit *>(this)->ComputeDepth();
349 /// getHeight - Return the height of this node, which is the length of the
350 /// maximum path down to any node with has no successors.
351 unsigned getHeight() const {
352 if (!isHeightCurrent) const_cast<SUnit *>(this)->ComputeHeight();
356 /// setDepthToAtLeast - If NewDepth is greater than this node's depth
357 /// value, set it to be the new depth value. This also recursively
358 /// marks successor nodes dirty.
359 void setDepthToAtLeast(unsigned NewDepth);
361 /// setDepthToAtLeast - If NewDepth is greater than this node's depth
362 /// value, set it to be the new height value. This also recursively
363 /// marks predecessor nodes dirty.
364 void setHeightToAtLeast(unsigned NewHeight);
366 /// setDepthDirty - Set a flag in this node to indicate that its
367 /// stored Depth value will require recomputation the next time
368 /// getDepth() is called.
369 void setDepthDirty();
371 /// setHeightDirty - Set a flag in this node to indicate that its
372 /// stored Height value will require recomputation the next time
373 /// getHeight() is called.
374 void setHeightDirty();
376 /// isPred - Test if node N is a predecessor of this node.
377 bool isPred(SUnit *N) {
378 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
379 if (Preds[i].getSUnit() == N)
384 /// isSucc - Test if node N is a successor of this node.
385 bool isSucc(SUnit *N) {
386 for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i)
387 if (Succs[i].getSUnit() == N)
392 void dump(const ScheduleDAG *G) const;
393 void dumpAll(const ScheduleDAG *G) const;
394 void print(raw_ostream &O, const ScheduleDAG *G) const;
398 void ComputeHeight();
401 //===--------------------------------------------------------------------===//
402 /// SchedulingPriorityQueue - This interface is used to plug different
403 /// priorities computation algorithms into the list scheduler. It implements
404 /// the interface of a standard priority queue, where nodes are inserted in
405 /// arbitrary order and returned in priority order. The computation of the
406 /// priority and the representation of the queue are totally up to the
407 /// implementation to decide.
409 class SchedulingPriorityQueue {
411 virtual ~SchedulingPriorityQueue() {}
413 virtual void initNodes(std::vector<SUnit> &SUnits) = 0;
414 virtual void addNode(const SUnit *SU) = 0;
415 virtual void updateNode(const SUnit *SU) = 0;
416 virtual void releaseState() = 0;
418 virtual unsigned size() const = 0;
419 virtual bool empty() const = 0;
420 virtual void push(SUnit *U) = 0;
422 virtual void push_all(const std::vector<SUnit *> &Nodes) = 0;
423 virtual SUnit *pop() = 0;
425 virtual void remove(SUnit *SU) = 0;
427 /// ScheduledNode - As each node is scheduled, this method is invoked. This
428 /// allows the priority function to adjust the priority of related
429 /// unscheduled nodes, for example.
431 virtual void ScheduledNode(SUnit *) {}
433 virtual void UnscheduledNode(SUnit *) {}
438 MachineBasicBlock *BB; // The block in which to insert instructions
439 MachineBasicBlock::iterator InsertPos;// The position to insert instructions
440 const TargetMachine &TM; // Target processor
441 const TargetInstrInfo *TII; // Target instruction information
442 const TargetRegisterInfo *TRI; // Target processor register info
443 const TargetLowering *TLI; // Target lowering info
444 MachineFunction &MF; // Machine function
445 MachineRegisterInfo &MRI; // Virtual/real register map
446 MachineConstantPool *ConstPool; // Target constant pool
447 std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s
448 // represent noop instructions.
449 std::vector<SUnit> SUnits; // The scheduling units.
450 SUnit EntrySU; // Special node for the region entry.
451 SUnit ExitSU; // Special node for the region exit.
453 explicit ScheduleDAG(MachineFunction &mf);
455 virtual ~ScheduleDAG();
457 /// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered
462 /// EmitSchedule - Insert MachineInstrs into the MachineBasicBlock
463 /// according to the order specified in Sequence.
465 virtual MachineBasicBlock*
466 EmitSchedule(DenseMap<MachineBasicBlock*, MachineBasicBlock*>*) = 0;
468 void dumpSchedule() const;
470 virtual void dumpNode(const SUnit *SU) const = 0;
472 /// getGraphNodeLabel - Return a label for an SUnit node in a visualization
473 /// of the ScheduleDAG.
474 virtual std::string getGraphNodeLabel(const SUnit *SU) const = 0;
476 /// addCustomGraphFeatures - Add custom features for a visualization of
478 virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {}
481 /// VerifySchedule - Verify that all SUnits were scheduled and that
482 /// their state is consistent.
483 void VerifySchedule(bool isBottomUp);
487 /// Run - perform scheduling.
489 void Run(MachineBasicBlock *bb, MachineBasicBlock::iterator insertPos);
491 /// BuildSchedGraph - Build SUnits and set up their Preds and Succs
492 /// to form the scheduling dependency graph.
494 virtual void BuildSchedGraph(AliasAnalysis *AA) = 0;
496 /// ComputeLatency - Compute node latency.
498 virtual void ComputeLatency(SUnit *SU) = 0;
500 /// ComputeOperandLatency - Override dependence edge latency using
501 /// operand use/def information
503 virtual void ComputeOperandLatency(SUnit *Def, SUnit *Use,
504 SDep& dep) const { };
506 /// Schedule - Order nodes according to selected style, filling
507 /// in the Sequence member.
509 virtual void Schedule() = 0;
511 /// ForceUnitLatencies - Return true if all scheduling edges should be given
512 /// a latency value of one. The default is to return false; schedulers may
513 /// override this as needed.
514 virtual bool ForceUnitLatencies() const { return false; }
516 /// EmitNoop - Emit a noop instruction.
520 void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap);
523 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
524 /// physical register has only a single copy use, then coalesced the copy
526 void EmitLiveInCopy(MachineBasicBlock *MBB,
527 MachineBasicBlock::iterator &InsertPos,
528 unsigned VirtReg, unsigned PhysReg,
529 const TargetRegisterClass *RC,
530 DenseMap<MachineInstr*, unsigned> &CopyRegMap);
532 /// EmitLiveInCopies - If this is the first basic block in the function,
533 /// and if it has live ins that need to be copied into vregs, emit the
534 /// copies into the top of the block.
535 void EmitLiveInCopies(MachineBasicBlock *MBB);
538 class SUnitIterator : public std::iterator<std::forward_iterator_tag,
543 SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {}
545 bool operator==(const SUnitIterator& x) const {
546 return Operand == x.Operand;
548 bool operator!=(const SUnitIterator& x) const { return !operator==(x); }
550 const SUnitIterator &operator=(const SUnitIterator &I) {
551 assert(I.Node==Node && "Cannot assign iterators to two different nodes!");
556 pointer operator*() const {
557 return Node->Preds[Operand].getSUnit();
559 pointer operator->() const { return operator*(); }
561 SUnitIterator& operator++() { // Preincrement
565 SUnitIterator operator++(int) { // Postincrement
566 SUnitIterator tmp = *this; ++*this; return tmp;
569 static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); }
570 static SUnitIterator end (SUnit *N) {
571 return SUnitIterator(N, (unsigned)N->Preds.size());
574 unsigned getOperand() const { return Operand; }
575 const SUnit *getNode() const { return Node; }
576 /// isCtrlDep - Test if this is not an SDep::Data dependence.
577 bool isCtrlDep() const {
578 return getSDep().isCtrl();
580 bool isArtificialDep() const {
581 return getSDep().isArtificial();
583 const SDep &getSDep() const {
584 return Node->Preds[Operand];
588 template <> struct GraphTraits<SUnit*> {
589 typedef SUnit NodeType;
590 typedef SUnitIterator ChildIteratorType;
591 static inline NodeType *getEntryNode(SUnit *N) { return N; }
592 static inline ChildIteratorType child_begin(NodeType *N) {
593 return SUnitIterator::begin(N);
595 static inline ChildIteratorType child_end(NodeType *N) {
596 return SUnitIterator::end(N);
600 template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> {
601 typedef std::vector<SUnit>::iterator nodes_iterator;
602 static nodes_iterator nodes_begin(ScheduleDAG *G) {
603 return G->SUnits.begin();
605 static nodes_iterator nodes_end(ScheduleDAG *G) {
606 return G->SUnits.end();
610 /// ScheduleDAGTopologicalSort is a class that computes a topological
611 /// ordering for SUnits and provides methods for dynamically updating
612 /// the ordering as new edges are added.
614 /// This allows a very fast implementation of IsReachable, for example.
616 class ScheduleDAGTopologicalSort {
617 /// SUnits - A reference to the ScheduleDAG's SUnits.
618 std::vector<SUnit> &SUnits;
620 /// Index2Node - Maps topological index to the node number.
621 std::vector<int> Index2Node;
622 /// Node2Index - Maps the node number to its topological index.
623 std::vector<int> Node2Index;
624 /// Visited - a set of nodes visited during a DFS traversal.
627 /// DFS - make a DFS traversal and mark all nodes affected by the
628 /// edge insertion. These nodes will later get new topological indexes
629 /// by means of the Shift method.
630 void DFS(const SUnit *SU, int UpperBound, bool& HasLoop);
632 /// Shift - reassign topological indexes for the nodes in the DAG
633 /// to preserve the topological ordering.
634 void Shift(BitVector& Visited, int LowerBound, int UpperBound);
636 /// Allocate - assign the topological index to the node n.
637 void Allocate(int n, int index);
640 explicit ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits);
642 /// InitDAGTopologicalSorting - create the initial topological
643 /// ordering from the DAG to be scheduled.
644 void InitDAGTopologicalSorting();
646 /// IsReachable - Checks if SU is reachable from TargetSU.
647 bool IsReachable(const SUnit *SU, const SUnit *TargetSU);
649 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU
650 /// will create a cycle.
651 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU);
653 /// AddPred - Updates the topological ordering to accomodate an edge
654 /// to be added from SUnit X to SUnit Y.
655 void AddPred(SUnit *Y, SUnit *X);
657 /// RemovePred - Updates the topological ordering to accomodate an
658 /// an edge to be removed from the specified node N from the predecessors
659 /// of the current node M.
660 void RemovePred(SUnit *M, SUnit *N);
662 typedef std::vector<int>::iterator iterator;
663 typedef std::vector<int>::const_iterator const_iterator;
664 iterator begin() { return Index2Node.begin(); }
665 const_iterator begin() const { return Index2Node.begin(); }
666 iterator end() { return Index2Node.end(); }
667 const_iterator end() const { return Index2Node.end(); }
669 typedef std::vector<int>::reverse_iterator reverse_iterator;
670 typedef std::vector<int>::const_reverse_iterator const_reverse_iterator;
671 reverse_iterator rbegin() { return Index2Node.rbegin(); }
672 const_reverse_iterator rbegin() const { return Index2Node.rbegin(); }
673 reverse_iterator rend() { return Index2Node.rend(); }
674 const_reverse_iterator rend() const { return Index2Node.rend(); }