1 //===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAG class, which is used as the common
11 // base class for instruction schedulers.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SCHEDULEDAG_H
16 #define LLVM_CODEGEN_SCHEDULEDAG_H
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/GraphTraits.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/PointerIntPair.h"
27 class MachineConstantPool;
28 class MachineFunction;
29 class MachineModuleInfo;
30 class MachineRegisterInfo;
32 class TargetRegisterInfo;
36 class TargetInstrInfo;
37 class TargetInstrDesc;
40 class TargetRegisterClass;
41 template<class Graph> class GraphWriter;
43 /// SDep - Scheduling dependency. This represents one direction of an
44 /// edge in the scheduling DAG.
47 /// Kind - These are the different kinds of scheduling dependencies.
49 Data, ///< Regular data dependence (aka true-dependence).
50 Anti, ///< A register anti-dependedence (aka WAR).
51 Output, ///< A register output-dependence (aka WAW).
52 Order ///< Any other ordering dependency.
56 /// Dep - A pointer to the depending/depended-on SUnit, and an enum
57 /// indicating the kind of the dependency.
58 PointerIntPair<SUnit *, 2, Kind> Dep;
60 /// Contents - A union discriminated by the dependence kind.
62 /// Reg - For Data, Anti, and Output dependencies, the associated
63 /// register. For Data dependencies that don't currently have a register
64 /// assigned, this is set to zero.
67 /// Order - Additional information about Order dependencies.
69 /// isNormalMemory - True if both sides of the dependence
70 /// access memory in non-volatile and fully modeled ways.
71 bool isNormalMemory : 1;
73 /// isMustAlias - True if both sides of the dependence are known to
74 /// access the same memory.
77 /// isArtificial - True if this is an artificial dependency, meaning
78 /// it is not necessary for program correctness, and may be safely
79 /// deleted if necessary.
80 bool isArtificial : 1;
84 /// Latency - The time associated with this edge. Often this is just
85 /// the value of the Latency field of the predecessor, however advanced
86 /// models may provide additional information about specific edges.
90 /// SDep - Construct a null SDep. This is only for use by container
91 /// classes which require default constructors. SUnits may not
92 /// have null SDep edges.
93 SDep() : Dep(0, Data) {}
95 /// SDep - Construct an SDep with the specified values.
96 SDep(SUnit *S, Kind kind, unsigned latency = 1, unsigned Reg = 0,
97 bool isNormalMemory = false, bool isMustAlias = false,
98 bool isArtificial = false)
99 : Dep(S, kind), Contents(), Latency(latency) {
104 "SDep::Anti and SDep::Output must use a non-zero Reg!");
107 assert(!isMustAlias && "isMustAlias only applies with SDep::Order!");
108 assert(!isArtificial && "isArtificial only applies with SDep::Order!");
112 assert(Reg == 0 && "Reg given for non-register dependence!");
113 Contents.Order.isNormalMemory = isNormalMemory;
114 Contents.Order.isMustAlias = isMustAlias;
115 Contents.Order.isArtificial = isArtificial;
120 bool operator==(const SDep &Other) const {
121 if (Dep != Other.Dep || Latency != Other.Latency) return false;
122 switch (Dep.getInt()) {
126 return Contents.Reg == Other.Contents.Reg;
128 return Contents.Order.isNormalMemory ==
129 Other.Contents.Order.isNormalMemory &&
130 Contents.Order.isMustAlias == Other.Contents.Order.isMustAlias &&
131 Contents.Order.isArtificial == Other.Contents.Order.isArtificial;
133 assert(0 && "Invalid dependency kind!");
137 bool operator!=(const SDep &Other) const {
138 return !operator==(Other);
141 /// getLatency - Return the latency value for this edge, which roughly
142 /// means the minimum number of cycles that must elapse between the
143 /// predecessor and the successor, given that they have this edge
145 unsigned getLatency() const {
149 //// getSUnit - Return the SUnit to which this edge points.
150 SUnit *getSUnit() const {
151 return Dep.getPointer();
154 //// setSUnit - Assign the SUnit to which this edge points.
155 void setSUnit(SUnit *SU) {
159 /// getKind - Return an enum value representing the kind of the dependence.
160 Kind getKind() const {
164 /// isCtrl - Shorthand for getKind() != SDep::Data.
165 bool isCtrl() const {
166 return getKind() != Data;
169 /// isNormalMemory - Test if this is an Order dependence between two
170 /// memory accesses where both sides of the dependence access memory
171 /// in non-volatile and fully modeled ways.
172 bool isNormalMemory() const {
173 return getKind() == Order && Contents.Order.isNormalMemory;
176 /// isMustAlias - Test if this is an Order dependence that is marked
177 /// as "must alias", meaning that the SUnits at either end of the edge
178 /// have a memory dependence on a known memory location.
179 bool isMustAlias() const {
180 return getKind() == Order && Contents.Order.isMustAlias;
183 /// isArtificial - Test if this is an Order dependence that is marked
184 /// as "artificial", meaning it isn't necessary for correctness.
185 bool isArtificial() const {
186 return getKind() == Order && Contents.Order.isArtificial;
189 /// isAssignedRegDep - Test if this is a Data dependence that is
190 /// associated with a register.
191 bool isAssignedRegDep() const {
192 return getKind() == Data && Contents.Reg != 0;
195 /// getReg - Return the register associated with this edge. This is
196 /// only valid on Data, Anti, and Output edges. On Data edges, this
197 /// value may be zero, meaning there is no associated register.
198 unsigned getReg() const {
199 assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
200 "getReg called on non-register dependence edge!");
204 /// setReg - Assign the associated register for this edge. This is
205 /// only valid on Data, Anti, and Output edges. On Anti and Output
206 /// edges, this value must not be zero. On Data edges, the value may
207 /// be zero, which would mean that no specific register is associated
209 void setReg(unsigned Reg) {
210 assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
211 "setReg called on non-register dependence edge!");
212 assert((getKind() != Anti || Reg != 0) &&
213 "SDep::Anti edge cannot use the zero register!");
214 assert((getKind() != Output || Reg != 0) &&
215 "SDep::Output edge cannot use the zero register!");
220 /// SUnit - Scheduling unit. This is a node in the scheduling DAG.
223 SDNode *Node; // Representative node.
224 MachineInstr *Instr; // Alternatively, a MachineInstr.
226 SUnit *OrigNode; // If not this, the node from which
227 // this node was cloned.
229 // Preds/Succs - The SUnits before/after us in the graph. The boolean value
230 // is true if the edge is a token chain edge, false if it is a value edge.
231 SmallVector<SDep, 4> Preds; // All sunit predecessors.
232 SmallVector<SDep, 4> Succs; // All sunit successors.
234 typedef SmallVector<SDep, 4>::iterator pred_iterator;
235 typedef SmallVector<SDep, 4>::iterator succ_iterator;
236 typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator;
237 typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator;
239 unsigned NodeNum; // Entry # of node in the node vector.
240 unsigned NodeQueueId; // Queue id of node.
241 unsigned short Latency; // Node latency.
242 short NumPreds; // # of SDep::Data preds.
243 short NumSuccs; // # of SDep::Data sucss.
244 short NumPredsLeft; // # of preds not scheduled.
245 short NumSuccsLeft; // # of succs not scheduled.
246 bool isTwoAddress : 1; // Is a two-address instruction.
247 bool isCommutable : 1; // Is a commutable instruction.
248 bool hasPhysRegDefs : 1; // Has physreg defs that are being used.
249 bool isPending : 1; // True once pending.
250 bool isAvailable : 1; // True once available.
251 bool isScheduled : 1; // True once scheduled.
252 bool isScheduleHigh : 1; // True if preferable to schedule high.
254 bool isDepthCurrent : 1; // True if Depth is current.
255 bool isHeightCurrent : 1; // True if Height is current.
256 unsigned Depth; // Node depth.
257 unsigned Height; // Node height.
259 const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null.
260 const TargetRegisterClass *CopySrcRC;
262 /// SUnit - Construct an SUnit for pre-regalloc scheduling to represent
263 /// an SDNode and any nodes flagged to it.
264 SUnit(SDNode *node, unsigned nodenum)
265 : Node(node), Instr(0), OrigNode(0), NodeNum(nodenum), NodeQueueId(0),
266 Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
267 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
268 isPending(false), isAvailable(false), isScheduled(false),
269 isScheduleHigh(false), isDepthCurrent(false), isHeightCurrent(false),
271 CopyDstRC(NULL), CopySrcRC(NULL) {}
273 /// SUnit - Construct an SUnit for post-regalloc scheduling to represent
275 SUnit(MachineInstr *instr, unsigned nodenum)
276 : Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum), NodeQueueId(0),
277 Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
278 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
279 isPending(false), isAvailable(false), isScheduled(false),
280 isScheduleHigh(false), isDepthCurrent(false), isHeightCurrent(false),
282 CopyDstRC(NULL), CopySrcRC(NULL) {}
284 /// setNode - Assign the representative SDNode for this SUnit.
285 /// This may be used during pre-regalloc scheduling.
286 void setNode(SDNode *N) {
287 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!");
291 /// getNode - Return the representative SDNode for this SUnit.
292 /// This may be used during pre-regalloc scheduling.
293 SDNode *getNode() const {
294 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!");
298 /// setInstr - Assign the instruction for the SUnit.
299 /// This may be used during post-regalloc scheduling.
300 void setInstr(MachineInstr *MI) {
301 assert(!Node && "Setting MachineInstr of SUnit with SDNode!");
305 /// getInstr - Return the representative MachineInstr for this SUnit.
306 /// This may be used during post-regalloc scheduling.
307 MachineInstr *getInstr() const {
308 assert(!Node && "Reading MachineInstr of SUnit with SDNode!");
312 /// addPred - This adds the specified edge as a pred of the current node if
313 /// not already. It also adds the current node as a successor of the
315 void addPred(const SDep &D);
317 /// removePred - This removes the specified edge as a pred of the current
318 /// node if it exists. It also removes the current node as a successor of
319 /// the specified node.
320 void removePred(const SDep &D);
322 /// getDepth - Return the depth of this node, which is the length of the
323 /// maximum path up to any node with has no predecessors.
324 unsigned getDepth() const {
325 if (!isDepthCurrent) const_cast<SUnit *>(this)->ComputeDepth();
329 /// getHeight - Return the height of this node, which is the length of the
330 /// maximum path down to any node with has no successors.
331 unsigned getHeight() const {
332 if (!isHeightCurrent) const_cast<SUnit *>(this)->ComputeHeight();
336 /// setDepthToAtLeast - If NewDepth is greater than this node's depth
337 /// value, set it to be the new depth value. This also recursively
338 /// marks successor nodes dirty.
339 void setDepthToAtLeast(unsigned NewDepth);
341 /// setDepthToAtLeast - If NewDepth is greater than this node's depth
342 /// value, set it to be the new height value. This also recursively
343 /// marks predecessor nodes dirty.
344 void setHeightToAtLeast(unsigned NewHeight);
346 /// setDepthDirty - Set a flag in this node to indicate that its
347 /// stored Depth value will require recomputation the next time
348 /// getDepth() is called.
349 void setDepthDirty();
351 /// setHeightDirty - Set a flag in this node to indicate that its
352 /// stored Height value will require recomputation the next time
353 /// getHeight() is called.
354 void setHeightDirty();
356 /// isPred - Test if node N is a predecessor of this node.
357 bool isPred(SUnit *N) {
358 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
359 if (Preds[i].getSUnit() == N)
364 /// isSucc - Test if node N is a successor of this node.
365 bool isSucc(SUnit *N) {
366 for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i)
367 if (Succs[i].getSUnit() == N)
372 void dump(const ScheduleDAG *G) const;
373 void dumpAll(const ScheduleDAG *G) const;
374 void print(raw_ostream &O, const ScheduleDAG *G) const;
378 void ComputeHeight();
381 //===--------------------------------------------------------------------===//
382 /// SchedulingPriorityQueue - This interface is used to plug different
383 /// priorities computation algorithms into the list scheduler. It implements
384 /// the interface of a standard priority queue, where nodes are inserted in
385 /// arbitrary order and returned in priority order. The computation of the
386 /// priority and the representation of the queue are totally up to the
387 /// implementation to decide.
389 class SchedulingPriorityQueue {
391 virtual ~SchedulingPriorityQueue() {}
393 virtual void initNodes(std::vector<SUnit> &SUnits) = 0;
394 virtual void addNode(const SUnit *SU) = 0;
395 virtual void updateNode(const SUnit *SU) = 0;
396 virtual void releaseState() = 0;
398 virtual unsigned size() const = 0;
399 virtual bool empty() const = 0;
400 virtual void push(SUnit *U) = 0;
402 virtual void push_all(const std::vector<SUnit *> &Nodes) = 0;
403 virtual SUnit *pop() = 0;
405 virtual void remove(SUnit *SU) = 0;
407 /// ScheduledNode - As each node is scheduled, this method is invoked. This
408 /// allows the priority function to adjust the priority of related
409 /// unscheduled nodes, for example.
411 virtual void ScheduledNode(SUnit *) {}
413 virtual void UnscheduledNode(SUnit *) {}
418 SelectionDAG *DAG; // DAG of the current basic block
419 MachineBasicBlock *BB; // Current basic block
420 const TargetMachine &TM; // Target processor
421 const TargetInstrInfo *TII; // Target instruction information
422 const TargetRegisterInfo *TRI; // Target processor register info
423 TargetLowering *TLI; // Target lowering info
424 MachineFunction *MF; // Machine function
425 MachineRegisterInfo &MRI; // Virtual/real register map
426 MachineConstantPool *ConstPool; // Target constant pool
427 std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s
428 // represent noop instructions.
429 std::vector<SUnit> SUnits; // The scheduling units.
431 ScheduleDAG(SelectionDAG *dag, MachineBasicBlock *bb,
432 const TargetMachine &tm);
434 virtual ~ScheduleDAG();
436 /// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered
441 /// Run - perform scheduling.
445 /// BuildSchedGraph - Build SUnits and set up their Preds and Succs
446 /// to form the scheduling dependency graph.
448 virtual void BuildSchedGraph() = 0;
450 /// ComputeLatency - Compute node latency.
452 virtual void ComputeLatency(SUnit *SU) = 0;
455 /// EmitNoop - Emit a noop instruction.
460 virtual MachineBasicBlock *EmitSchedule() = 0;
462 void dumpSchedule() const;
464 /// Schedule - Order nodes according to selected style, filling
465 /// in the Sequence member.
467 virtual void Schedule() = 0;
469 virtual void dumpNode(const SUnit *SU) const = 0;
471 /// getGraphNodeLabel - Return a label for an SUnit node in a visualization
472 /// of the ScheduleDAG.
473 virtual std::string getGraphNodeLabel(const SUnit *SU) const = 0;
475 /// addCustomGraphFeatures - Add custom features for a visualization of
477 virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {}
480 /// VerifySchedule - Verify that all SUnits were scheduled and that
481 /// their state is consistent.
482 void VerifySchedule(bool isBottomUp);
486 void AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO);
488 void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap);
490 /// ForceUnitLatencies - Return true if all scheduling edges should be given a
491 /// latency value of one. The default is to return false; schedulers may
492 /// override this as needed.
493 virtual bool ForceUnitLatencies() const { return false; }
496 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
497 /// physical register has only a single copy use, then coalesced the copy
499 void EmitLiveInCopy(MachineBasicBlock *MBB,
500 MachineBasicBlock::iterator &InsertPos,
501 unsigned VirtReg, unsigned PhysReg,
502 const TargetRegisterClass *RC,
503 DenseMap<MachineInstr*, unsigned> &CopyRegMap);
505 /// EmitLiveInCopies - If this is the first basic block in the function,
506 /// and if it has live ins that need to be copied into vregs, emit the
507 /// copies into the top of the block.
508 void EmitLiveInCopies(MachineBasicBlock *MBB);
511 class SUnitIterator : public forward_iterator<SUnit, ptrdiff_t> {
515 SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {}
517 bool operator==(const SUnitIterator& x) const {
518 return Operand == x.Operand;
520 bool operator!=(const SUnitIterator& x) const { return !operator==(x); }
522 const SUnitIterator &operator=(const SUnitIterator &I) {
523 assert(I.Node == Node && "Cannot assign iterators to two different nodes!");
528 pointer operator*() const {
529 return Node->Preds[Operand].getSUnit();
531 pointer operator->() const { return operator*(); }
533 SUnitIterator& operator++() { // Preincrement
537 SUnitIterator operator++(int) { // Postincrement
538 SUnitIterator tmp = *this; ++*this; return tmp;
541 static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); }
542 static SUnitIterator end (SUnit *N) {
543 return SUnitIterator(N, (unsigned)N->Preds.size());
546 unsigned getOperand() const { return Operand; }
547 const SUnit *getNode() const { return Node; }
548 /// isCtrlDep - Test if this is not an SDep::Data dependence.
549 bool isCtrlDep() const {
550 return getSDep().isCtrl();
552 bool isArtificialDep() const {
553 return getSDep().isArtificial();
555 const SDep &getSDep() const {
556 return Node->Preds[Operand];
560 template <> struct GraphTraits<SUnit*> {
561 typedef SUnit NodeType;
562 typedef SUnitIterator ChildIteratorType;
563 static inline NodeType *getEntryNode(SUnit *N) { return N; }
564 static inline ChildIteratorType child_begin(NodeType *N) {
565 return SUnitIterator::begin(N);
567 static inline ChildIteratorType child_end(NodeType *N) {
568 return SUnitIterator::end(N);
572 template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> {
573 typedef std::vector<SUnit>::iterator nodes_iterator;
574 static nodes_iterator nodes_begin(ScheduleDAG *G) {
575 return G->SUnits.begin();
577 static nodes_iterator nodes_end(ScheduleDAG *G) {
578 return G->SUnits.end();
582 /// ScheduleDAGTopologicalSort is a class that computes a topological
583 /// ordering for SUnits and provides methods for dynamically updating
584 /// the ordering as new edges are added.
586 /// This allows a very fast implementation of IsReachable, for example.
588 class ScheduleDAGTopologicalSort {
589 /// SUnits - A reference to the ScheduleDAG's SUnits.
590 std::vector<SUnit> &SUnits;
592 /// Index2Node - Maps topological index to the node number.
593 std::vector<int> Index2Node;
594 /// Node2Index - Maps the node number to its topological index.
595 std::vector<int> Node2Index;
596 /// Visited - a set of nodes visited during a DFS traversal.
599 /// DFS - make a DFS traversal and mark all nodes affected by the
600 /// edge insertion. These nodes will later get new topological indexes
601 /// by means of the Shift method.
602 void DFS(const SUnit *SU, int UpperBound, bool& HasLoop);
604 /// Shift - reassign topological indexes for the nodes in the DAG
605 /// to preserve the topological ordering.
606 void Shift(BitVector& Visited, int LowerBound, int UpperBound);
608 /// Allocate - assign the topological index to the node n.
609 void Allocate(int n, int index);
612 explicit ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits);
614 /// InitDAGTopologicalSorting - create the initial topological
615 /// ordering from the DAG to be scheduled.
616 void InitDAGTopologicalSorting();
618 /// IsReachable - Checks if SU is reachable from TargetSU.
619 bool IsReachable(const SUnit *SU, const SUnit *TargetSU);
621 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU
622 /// will create a cycle.
623 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU);
625 /// AddPred - Updates the topological ordering to accomodate an edge
626 /// to be added from SUnit X to SUnit Y.
627 void AddPred(SUnit *Y, SUnit *X);
629 /// RemovePred - Updates the topological ordering to accomodate an
630 /// an edge to be removed from the specified node N from the predecessors
631 /// of the current node M.
632 void RemovePred(SUnit *M, SUnit *N);
634 typedef std::vector<int>::iterator iterator;
635 typedef std::vector<int>::const_iterator const_iterator;
636 iterator begin() { return Index2Node.begin(); }
637 const_iterator begin() const { return Index2Node.begin(); }
638 iterator end() { return Index2Node.end(); }
639 const_iterator end() const { return Index2Node.end(); }
641 typedef std::vector<int>::reverse_iterator reverse_iterator;
642 typedef std::vector<int>::const_reverse_iterator const_reverse_iterator;
643 reverse_iterator rbegin() { return Index2Node.rbegin(); }
644 const_reverse_iterator rbegin() const { return Index2Node.rbegin(); }
645 reverse_iterator rend() { return Index2Node.rend(); }
646 const_reverse_iterator rend() const { return Index2Node.rend(); }