1 //===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAG class, which is used as the common
11 // base class for instruction schedulers. This encapsulates the scheduling DAG,
12 // which is shared between SelectionDAG and MachineInstr scheduling.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_SCHEDULEDAG_H
17 #define LLVM_CODEGEN_SCHEDULEDAG_H
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/GraphTraits.h"
22 #include "llvm/ADT/PointerIntPair.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/CodeGen/MachineBasicBlock.h"
25 #include "llvm/Target/TargetLowering.h"
30 class MachineConstantPool;
31 class MachineFunction;
32 class MachineRegisterInfo;
34 struct MCSchedClassDesc;
35 class TargetRegisterInfo;
38 class TargetInstrInfo;
41 class TargetRegisterClass;
42 template<class Graph> class GraphWriter;
44 /// SDep - Scheduling dependency. This represents one direction of an
45 /// edge in the scheduling DAG.
48 /// Kind - These are the different kinds of scheduling dependencies.
50 Data, ///< Regular data dependence (aka true-dependence).
51 Anti, ///< A register anti-dependedence (aka WAR).
52 Output, ///< A register output-dependence (aka WAW).
53 Order ///< Any other ordering dependency.
57 Barrier, ///< An unknown scheduling barrier.
58 MayAliasMem, ///< Nonvolatile load/Store instructions that may alias.
59 MustAliasMem, ///< Nonvolatile load/Store instructions that must alias.
60 Artificial, ///< Arbitrary weak DAG edge (no actual dependence).
61 Cluster ///< Weak DAG edge linking a chain of clustered instrs.
65 /// Dep - A pointer to the depending/depended-on SUnit, and an enum
66 /// indicating the kind of the dependency.
67 PointerIntPair<SUnit *, 2, Kind> Dep;
69 /// Contents - A union discriminated by the dependence kind.
71 /// Reg - For Data, Anti, and Output dependencies, the associated
72 /// register. For Data dependencies that don't currently have a register
73 /// assigned, this is set to zero.
76 /// Order - Additional information about Order dependencies.
77 unsigned OrdKind; // enum OrderKind
80 /// Latency - The time associated with this edge. Often this is just
81 /// the value of the Latency field of the predecessor, however advanced
82 /// models may provide additional information about specific edges.
84 /// Record MinLatency seperately from "expected" Latency.
86 /// FIXME: this field is not packed on LP64. Convert to 16-bit DAG edge
87 /// latency after introducing saturating truncation.
91 /// SDep - Construct a null SDep. This is only for use by container
92 /// classes which require default constructors. SUnits may not
93 /// have null SDep edges.
94 SDep() : Dep(0, Data) {}
96 /// SDep - Construct an SDep with the specified values.
97 SDep(SUnit *S, Kind kind, unsigned Reg)
98 : Dep(S, kind), Contents() {
101 llvm_unreachable("Reg given for non-register dependence!");
105 "SDep::Anti and SDep::Output must use a non-zero Reg!");
114 MinLatency = Latency;
116 SDep(SUnit *S, OrderKind kind)
117 : Dep(S, Order), Contents(), Latency(0), MinLatency(0) {
118 Contents.OrdKind = kind;
121 /// Return true if the specified SDep is equivalent except for latency.
122 bool overlaps(const SDep &Other) const {
123 if (Dep != Other.Dep) return false;
124 switch (Dep.getInt()) {
128 return Contents.Reg == Other.Contents.Reg;
130 return Contents.OrdKind == Other.Contents.OrdKind;
132 llvm_unreachable("Invalid dependency kind!");
135 bool operator==(const SDep &Other) const {
136 return overlaps(Other)
137 && Latency == Other.Latency && MinLatency == Other.MinLatency;
140 bool operator!=(const SDep &Other) const {
141 return !operator==(Other);
144 /// getLatency - Return the latency value for this edge, which roughly
145 /// means the minimum number of cycles that must elapse between the
146 /// predecessor and the successor, given that they have this edge
148 unsigned getLatency() const {
152 /// setLatency - Set the latency for this edge.
153 void setLatency(unsigned Lat) {
157 /// getMinLatency - Return the minimum latency for this edge. Minimum
158 /// latency is used for scheduling groups, while normal (expected) latency
159 /// is for instruction cost and critical path.
160 unsigned getMinLatency() const {
164 /// setMinLatency - Set the minimum latency for this edge.
165 void setMinLatency(unsigned Lat) {
169 //// getSUnit - Return the SUnit to which this edge points.
170 SUnit *getSUnit() const {
171 return Dep.getPointer();
174 //// setSUnit - Assign the SUnit to which this edge points.
175 void setSUnit(SUnit *SU) {
179 /// getKind - Return an enum value representing the kind of the dependence.
180 Kind getKind() const {
184 /// isCtrl - Shorthand for getKind() != SDep::Data.
185 bool isCtrl() const {
186 return getKind() != Data;
189 /// isNormalMemory - Test if this is an Order dependence between two
190 /// memory accesses where both sides of the dependence access memory
191 /// in non-volatile and fully modeled ways.
192 bool isNormalMemory() const {
193 return getKind() == Order && (Contents.OrdKind == MayAliasMem
194 || Contents.OrdKind == MustAliasMem);
197 /// isMustAlias - Test if this is an Order dependence that is marked
198 /// as "must alias", meaning that the SUnits at either end of the edge
199 /// have a memory dependence on a known memory location.
200 bool isMustAlias() const {
201 return getKind() == Order && Contents.OrdKind == MustAliasMem;
204 /// isWeak - Test if this a weak dependence. Weak dependencies are
205 /// considered DAG edges for height computation and other heuristics, but do
206 /// not force ordering. Breaking a weak edge may require the scheduler to
207 /// compensate, for example by inserting a copy.
208 bool isWeak() const {
209 return getKind() == Order && Contents.OrdKind == Cluster;
212 /// isArtificial - Test if this is an Order dependence that is marked
213 /// as "artificial", meaning it isn't necessary for correctness.
214 bool isArtificial() const {
215 return getKind() == Order && Contents.OrdKind == Artificial;
218 /// isCluster - Test if this is an Order dependence that is marked
219 /// as "cluster", meaning it is artificial and wants to be adjacent.
220 bool isCluster() const {
221 return getKind() == Order && Contents.OrdKind == Cluster;
224 /// isAssignedRegDep - Test if this is a Data dependence that is
225 /// associated with a register.
226 bool isAssignedRegDep() const {
227 return getKind() == Data && Contents.Reg != 0;
230 /// getReg - Return the register associated with this edge. This is
231 /// only valid on Data, Anti, and Output edges. On Data edges, this
232 /// value may be zero, meaning there is no associated register.
233 unsigned getReg() const {
234 assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
235 "getReg called on non-register dependence edge!");
239 /// setReg - Assign the associated register for this edge. This is
240 /// only valid on Data, Anti, and Output edges. On Anti and Output
241 /// edges, this value must not be zero. On Data edges, the value may
242 /// be zero, which would mean that no specific register is associated
244 void setReg(unsigned Reg) {
245 assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
246 "setReg called on non-register dependence edge!");
247 assert((getKind() != Anti || Reg != 0) &&
248 "SDep::Anti edge cannot use the zero register!");
249 assert((getKind() != Output || Reg != 0) &&
250 "SDep::Output edge cannot use the zero register!");
256 struct isPodLike<SDep> { static const bool value = true; };
258 /// SUnit - Scheduling unit. This is a node in the scheduling DAG.
261 SDNode *Node; // Representative node.
262 MachineInstr *Instr; // Alternatively, a MachineInstr.
264 SUnit *OrigNode; // If not this, the node from which
265 // this node was cloned.
266 // (SD scheduling only)
268 const MCSchedClassDesc *SchedClass; // NULL or resolved SchedClass.
270 // Preds/Succs - The SUnits before/after us in the graph.
271 SmallVector<SDep, 4> Preds; // All sunit predecessors.
272 SmallVector<SDep, 4> Succs; // All sunit successors.
274 typedef SmallVector<SDep, 4>::iterator pred_iterator;
275 typedef SmallVector<SDep, 4>::iterator succ_iterator;
276 typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator;
277 typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator;
279 unsigned NodeNum; // Entry # of node in the node vector.
280 unsigned NodeQueueId; // Queue id of node.
281 unsigned NumPreds; // # of SDep::Data preds.
282 unsigned NumSuccs; // # of SDep::Data sucss.
283 unsigned NumPredsLeft; // # of preds not scheduled.
284 unsigned NumSuccsLeft; // # of succs not scheduled.
285 unsigned WeakPredsLeft; // # of weak preds not scheduled.
286 unsigned WeakSuccsLeft; // # of weak succs not scheduled.
287 unsigned short NumRegDefsLeft; // # of reg defs with no scheduled use.
288 unsigned short Latency; // Node latency.
289 bool isVRegCycle : 1; // May use and def the same vreg.
290 bool isCall : 1; // Is a function call.
291 bool isCallOp : 1; // Is a function call operand.
292 bool isTwoAddress : 1; // Is a two-address instruction.
293 bool isCommutable : 1; // Is a commutable instruction.
294 bool hasPhysRegDefs : 1; // Has physreg defs that are being used.
295 bool hasPhysRegClobbers : 1; // Has any physreg defs, used or not.
296 bool isPending : 1; // True once pending.
297 bool isAvailable : 1; // True once available.
298 bool isScheduled : 1; // True once scheduled.
299 bool isScheduleHigh : 1; // True if preferable to schedule high.
300 bool isScheduleLow : 1; // True if preferable to schedule low.
301 bool isCloned : 1; // True if this node has been cloned.
302 Sched::Preference SchedulingPref; // Scheduling preference.
305 bool isDepthCurrent : 1; // True if Depth is current.
306 bool isHeightCurrent : 1; // True if Height is current.
307 unsigned Depth; // Node depth.
308 unsigned Height; // Node height.
310 unsigned TopReadyCycle; // Cycle relative to start when node is ready.
311 unsigned BotReadyCycle; // Cycle relative to end when node is ready.
313 const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null.
314 const TargetRegisterClass *CopySrcRC;
316 /// SUnit - Construct an SUnit for pre-regalloc scheduling to represent
317 /// an SDNode and any nodes flagged to it.
318 SUnit(SDNode *node, unsigned nodenum)
319 : Node(node), Instr(0), OrigNode(0), SchedClass(0), NodeNum(nodenum),
320 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
321 NumSuccsLeft(0), WeakPredsLeft(0), WeakSuccsLeft(0), NumRegDefsLeft(0),
322 Latency(0), isVRegCycle(false), isCall(false), isCallOp(false),
323 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
324 hasPhysRegClobbers(false), isPending(false), isAvailable(false),
325 isScheduled(false), isScheduleHigh(false), isScheduleLow(false),
326 isCloned(false), SchedulingPref(Sched::None),
327 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
328 TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {}
330 /// SUnit - Construct an SUnit for post-regalloc scheduling to represent
332 SUnit(MachineInstr *instr, unsigned nodenum)
333 : Node(0), Instr(instr), OrigNode(0), SchedClass(0), NodeNum(nodenum),
334 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
335 NumSuccsLeft(0), WeakPredsLeft(0), WeakSuccsLeft(0), NumRegDefsLeft(0),
336 Latency(0), isVRegCycle(false), isCall(false), isCallOp(false),
337 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
338 hasPhysRegClobbers(false), isPending(false), isAvailable(false),
339 isScheduled(false), isScheduleHigh(false), isScheduleLow(false),
340 isCloned(false), SchedulingPref(Sched::None),
341 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
342 TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {}
344 /// SUnit - Construct a placeholder SUnit.
346 : Node(0), Instr(0), OrigNode(0), SchedClass(0), NodeNum(~0u),
347 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
348 NumSuccsLeft(0), WeakPredsLeft(0), WeakSuccsLeft(0), NumRegDefsLeft(0),
349 Latency(0), isVRegCycle(false), isCall(false), isCallOp(false),
350 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
351 hasPhysRegClobbers(false), isPending(false), isAvailable(false),
352 isScheduled(false), isScheduleHigh(false), isScheduleLow(false),
353 isCloned(false), SchedulingPref(Sched::None),
354 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
355 TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {}
357 /// setNode - Assign the representative SDNode for this SUnit.
358 /// This may be used during pre-regalloc scheduling.
359 void setNode(SDNode *N) {
360 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!");
364 /// getNode - Return the representative SDNode for this SUnit.
365 /// This may be used during pre-regalloc scheduling.
366 SDNode *getNode() const {
367 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!");
371 /// isInstr - Return true if this SUnit refers to a machine instruction as
372 /// opposed to an SDNode.
373 bool isInstr() const { return Instr; }
375 /// setInstr - Assign the instruction for the SUnit.
376 /// This may be used during post-regalloc scheduling.
377 void setInstr(MachineInstr *MI) {
378 assert(!Node && "Setting MachineInstr of SUnit with SDNode!");
382 /// getInstr - Return the representative MachineInstr for this SUnit.
383 /// This may be used during post-regalloc scheduling.
384 MachineInstr *getInstr() const {
385 assert(!Node && "Reading MachineInstr of SUnit with SDNode!");
389 /// addPred - This adds the specified edge as a pred of the current node if
390 /// not already. It also adds the current node as a successor of the
392 bool addPred(const SDep &D, bool Required = true);
394 /// removePred - This removes the specified edge as a pred of the current
395 /// node if it exists. It also removes the current node as a successor of
396 /// the specified node.
397 void removePred(const SDep &D);
399 /// getDepth - Return the depth of this node, which is the length of the
400 /// maximum path up to any node which has no predecessors.
401 unsigned getDepth() const {
403 const_cast<SUnit *>(this)->ComputeDepth();
407 /// getHeight - Return the height of this node, which is the length of the
408 /// maximum path down to any node which has no successors.
409 unsigned getHeight() const {
410 if (!isHeightCurrent)
411 const_cast<SUnit *>(this)->ComputeHeight();
415 /// setDepthToAtLeast - If NewDepth is greater than this node's
416 /// depth value, set it to be the new depth value. This also
417 /// recursively marks successor nodes dirty.
418 void setDepthToAtLeast(unsigned NewDepth);
420 /// setDepthToAtLeast - If NewDepth is greater than this node's
421 /// depth value, set it to be the new height value. This also
422 /// recursively marks predecessor nodes dirty.
423 void setHeightToAtLeast(unsigned NewHeight);
425 /// setDepthDirty - Set a flag in this node to indicate that its
426 /// stored Depth value will require recomputation the next time
427 /// getDepth() is called.
428 void setDepthDirty();
430 /// setHeightDirty - Set a flag in this node to indicate that its
431 /// stored Height value will require recomputation the next time
432 /// getHeight() is called.
433 void setHeightDirty();
435 /// isPred - Test if node N is a predecessor of this node.
436 bool isPred(SUnit *N) {
437 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
438 if (Preds[i].getSUnit() == N)
443 /// isSucc - Test if node N is a successor of this node.
444 bool isSucc(SUnit *N) {
445 for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i)
446 if (Succs[i].getSUnit() == N)
451 bool isTopReady() const {
452 return NumPredsLeft == 0;
454 bool isBottomReady() const {
455 return NumSuccsLeft == 0;
458 void dump(const ScheduleDAG *G) const;
459 void dumpAll(const ScheduleDAG *G) const;
460 void print(raw_ostream &O, const ScheduleDAG *G) const;
464 void ComputeHeight();
467 //===--------------------------------------------------------------------===//
468 /// SchedulingPriorityQueue - This interface is used to plug different
469 /// priorities computation algorithms into the list scheduler. It implements
470 /// the interface of a standard priority queue, where nodes are inserted in
471 /// arbitrary order and returned in priority order. The computation of the
472 /// priority and the representation of the queue are totally up to the
473 /// implementation to decide.
475 class SchedulingPriorityQueue {
476 virtual void anchor();
480 SchedulingPriorityQueue(bool rf = false):
481 CurCycle(0), HasReadyFilter(rf) {}
482 virtual ~SchedulingPriorityQueue() {}
484 virtual bool isBottomUp() const = 0;
486 virtual void initNodes(std::vector<SUnit> &SUnits) = 0;
487 virtual void addNode(const SUnit *SU) = 0;
488 virtual void updateNode(const SUnit *SU) = 0;
489 virtual void releaseState() = 0;
491 virtual bool empty() const = 0;
493 bool hasReadyFilter() const { return HasReadyFilter; }
495 virtual bool tracksRegPressure() const { return false; }
497 virtual bool isReady(SUnit *) const {
498 assert(!HasReadyFilter && "The ready filter must override isReady()");
501 virtual void push(SUnit *U) = 0;
503 void push_all(const std::vector<SUnit *> &Nodes) {
504 for (std::vector<SUnit *>::const_iterator I = Nodes.begin(),
505 E = Nodes.end(); I != E; ++I)
509 virtual SUnit *pop() = 0;
511 virtual void remove(SUnit *SU) = 0;
513 virtual void dump(ScheduleDAG *) const {}
515 /// scheduledNode - As each node is scheduled, this method is invoked. This
516 /// allows the priority function to adjust the priority of related
517 /// unscheduled nodes, for example.
519 virtual void scheduledNode(SUnit *) {}
521 virtual void unscheduledNode(SUnit *) {}
523 void setCurCycle(unsigned Cycle) {
527 unsigned getCurCycle() const {
534 const TargetMachine &TM; // Target processor
535 const TargetInstrInfo *TII; // Target instruction information
536 const TargetRegisterInfo *TRI; // Target processor register info
537 MachineFunction &MF; // Machine function
538 MachineRegisterInfo &MRI; // Virtual/real register map
539 std::vector<SUnit> SUnits; // The scheduling units.
540 SUnit EntrySU; // Special node for the region entry.
541 SUnit ExitSU; // Special node for the region exit.
544 static const bool StressSched = false;
549 explicit ScheduleDAG(MachineFunction &mf);
551 virtual ~ScheduleDAG();
553 /// clearDAG - clear the DAG state (between regions).
556 /// getInstrDesc - Return the MCInstrDesc of this SUnit.
557 /// Return NULL for SDNodes without a machine opcode.
558 const MCInstrDesc *getInstrDesc(const SUnit *SU) const {
559 if (SU->isInstr()) return &SU->getInstr()->getDesc();
560 return getNodeDesc(SU->getNode());
563 /// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered
566 void viewGraph(const Twine &Name, const Twine &Title);
569 virtual void dumpNode(const SUnit *SU) const = 0;
571 /// getGraphNodeLabel - Return a label for an SUnit node in a visualization
572 /// of the ScheduleDAG.
573 virtual std::string getGraphNodeLabel(const SUnit *SU) const = 0;
575 /// getDAGLabel - Return a label for the region of code covered by the DAG.
576 virtual std::string getDAGName() const = 0;
578 /// addCustomGraphFeatures - Add custom features for a visualization of
580 virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {}
583 /// VerifyScheduledDAG - Verify that all SUnits were scheduled and that
584 /// their state is consistent. Return the number of scheduled SUnits.
585 unsigned VerifyScheduledDAG(bool isBottomUp);
589 // Return the MCInstrDesc of this SDNode or NULL.
590 const MCInstrDesc *getNodeDesc(const SDNode *Node) const;
593 class SUnitIterator : public std::iterator<std::forward_iterator_tag,
598 SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {}
600 bool operator==(const SUnitIterator& x) const {
601 return Operand == x.Operand;
603 bool operator!=(const SUnitIterator& x) const { return !operator==(x); }
605 const SUnitIterator &operator=(const SUnitIterator &I) {
606 assert(I.Node==Node && "Cannot assign iterators to two different nodes!");
611 pointer operator*() const {
612 return Node->Preds[Operand].getSUnit();
614 pointer operator->() const { return operator*(); }
616 SUnitIterator& operator++() { // Preincrement
620 SUnitIterator operator++(int) { // Postincrement
621 SUnitIterator tmp = *this; ++*this; return tmp;
624 static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); }
625 static SUnitIterator end (SUnit *N) {
626 return SUnitIterator(N, (unsigned)N->Preds.size());
629 unsigned getOperand() const { return Operand; }
630 const SUnit *getNode() const { return Node; }
631 /// isCtrlDep - Test if this is not an SDep::Data dependence.
632 bool isCtrlDep() const {
633 return getSDep().isCtrl();
635 bool isArtificialDep() const {
636 return getSDep().isArtificial();
638 const SDep &getSDep() const {
639 return Node->Preds[Operand];
643 template <> struct GraphTraits<SUnit*> {
644 typedef SUnit NodeType;
645 typedef SUnitIterator ChildIteratorType;
646 static inline NodeType *getEntryNode(SUnit *N) { return N; }
647 static inline ChildIteratorType child_begin(NodeType *N) {
648 return SUnitIterator::begin(N);
650 static inline ChildIteratorType child_end(NodeType *N) {
651 return SUnitIterator::end(N);
655 template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> {
656 typedef std::vector<SUnit>::iterator nodes_iterator;
657 static nodes_iterator nodes_begin(ScheduleDAG *G) {
658 return G->SUnits.begin();
660 static nodes_iterator nodes_end(ScheduleDAG *G) {
661 return G->SUnits.end();
665 /// ScheduleDAGTopologicalSort is a class that computes a topological
666 /// ordering for SUnits and provides methods for dynamically updating
667 /// the ordering as new edges are added.
669 /// This allows a very fast implementation of IsReachable, for example.
671 class ScheduleDAGTopologicalSort {
672 /// SUnits - A reference to the ScheduleDAG's SUnits.
673 std::vector<SUnit> &SUnits;
676 /// Index2Node - Maps topological index to the node number.
677 std::vector<int> Index2Node;
678 /// Node2Index - Maps the node number to its topological index.
679 std::vector<int> Node2Index;
680 /// Visited - a set of nodes visited during a DFS traversal.
683 /// DFS - make a DFS traversal and mark all nodes affected by the
684 /// edge insertion. These nodes will later get new topological indexes
685 /// by means of the Shift method.
686 void DFS(const SUnit *SU, int UpperBound, bool& HasLoop);
688 /// Shift - reassign topological indexes for the nodes in the DAG
689 /// to preserve the topological ordering.
690 void Shift(BitVector& Visited, int LowerBound, int UpperBound);
692 /// Allocate - assign the topological index to the node n.
693 void Allocate(int n, int index);
696 ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits, SUnit *ExitSU);
698 /// InitDAGTopologicalSorting - create the initial topological
699 /// ordering from the DAG to be scheduled.
700 void InitDAGTopologicalSorting();
702 /// IsReachable - Checks if SU is reachable from TargetSU.
703 bool IsReachable(const SUnit *SU, const SUnit *TargetSU);
705 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU
706 /// will create a cycle.
707 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU);
709 /// AddPred - Updates the topological ordering to accommodate an edge
710 /// to be added from SUnit X to SUnit Y.
711 void AddPred(SUnit *Y, SUnit *X);
713 /// RemovePred - Updates the topological ordering to accommodate an
714 /// an edge to be removed from the specified node N from the predecessors
715 /// of the current node M.
716 void RemovePred(SUnit *M, SUnit *N);
718 typedef std::vector<int>::iterator iterator;
719 typedef std::vector<int>::const_iterator const_iterator;
720 iterator begin() { return Index2Node.begin(); }
721 const_iterator begin() const { return Index2Node.begin(); }
722 iterator end() { return Index2Node.end(); }
723 const_iterator end() const { return Index2Node.end(); }
725 typedef std::vector<int>::reverse_iterator reverse_iterator;
726 typedef std::vector<int>::const_reverse_iterator const_reverse_iterator;
727 reverse_iterator rbegin() { return Index2Node.rbegin(); }
728 const_reverse_iterator rbegin() const { return Index2Node.rbegin(); }
729 reverse_iterator rend() { return Index2Node.rend(); }
730 const_reverse_iterator rend() const { return Index2Node.rend(); }