1 //===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAG class, which is used as the common
11 // base class for SelectionDAG-based instruction scheduler.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SCHEDULEDAG_H
16 #define LLVM_CODEGEN_SCHEDULEDAG_H
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/GraphTraits.h"
22 #include "llvm/ADT/SmallSet.h"
27 class MachineConstantPool;
28 class MachineFunction;
29 class MachineModuleInfo;
30 class MachineRegisterInfo;
32 class TargetRegisterInfo;
34 class SelectionDAGISel;
35 class TargetInstrInfo;
36 class TargetInstrDesc;
39 class TargetRegisterClass;
41 /// HazardRecognizer - This determines whether or not an instruction can be
42 /// issued this cycle, and whether or not a noop needs to be inserted to handle
44 class HazardRecognizer {
46 virtual ~HazardRecognizer();
49 NoHazard, // This instruction can be emitted at this cycle.
50 Hazard, // This instruction can't be emitted at this cycle.
51 NoopHazard // This instruction can't be emitted, and needs noops.
54 /// getHazardType - Return the hazard type of emitting this node. There are
55 /// three possible results. Either:
56 /// * NoHazard: it is legal to issue this instruction on this cycle.
57 /// * Hazard: issuing this instruction would stall the machine. If some
58 /// other instruction is available, issue it first.
59 /// * NoopHazard: issuing this instruction would break the program. If
60 /// some other instruction can be issued, do so, otherwise issue a noop.
61 virtual HazardType getHazardType(SDNode *) {
65 /// EmitInstruction - This callback is invoked when an instruction is
66 /// emitted, to advance the hazard state.
67 virtual void EmitInstruction(SDNode *) {}
69 /// AdvanceCycle - This callback is invoked when no instructions can be
70 /// issued on this cycle without a hazard. This should increment the
71 /// internal state of the hazard recognizer so that previously "Hazard"
72 /// instructions will now not be hazards.
73 virtual void AdvanceCycle() {}
75 /// EmitNoop - This callback is invoked when a noop was added to the
76 /// instruction stream.
77 virtual void EmitNoop() {}
80 /// SDep - Scheduling dependency. It keeps track of dependent nodes,
81 /// cost of the depdenency, etc.
83 SUnit *Dep; // Dependent - either a predecessor or a successor.
84 unsigned Reg; // If non-zero, this dep is a phy register dependency.
85 int Cost; // Cost of the dependency.
86 bool isCtrl : 1; // True iff it's a control dependency.
87 bool isSpecial : 1; // True iff it's a special ctrl dep added during sched.
88 SDep(SUnit *d, unsigned r, int t, bool c, bool s)
89 : Dep(d), Reg(r), Cost(t), isCtrl(c), isSpecial(s) {}
92 /// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
93 /// a group of nodes flagged together.
95 SDNode *Node; // Representative node.
96 SmallVector<SDNode*,4> FlaggedNodes;// All nodes flagged to Node.
97 SUnit *OrigNode; // If not this, the node from which
98 // this node was cloned.
100 // Preds/Succs - The SUnits before/after us in the graph. The boolean value
101 // is true if the edge is a token chain edge, false if it is a value edge.
102 SmallVector<SDep, 4> Preds; // All sunit predecessors.
103 SmallVector<SDep, 4> Succs; // All sunit successors.
105 typedef SmallVector<SDep, 4>::iterator pred_iterator;
106 typedef SmallVector<SDep, 4>::iterator succ_iterator;
107 typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator;
108 typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator;
110 unsigned NodeNum; // Entry # of node in the node vector.
111 unsigned NodeQueueId; // Queue id of node.
112 unsigned short Latency; // Node latency.
113 short NumPreds; // # of preds.
114 short NumSuccs; // # of sucss.
115 short NumPredsLeft; // # of preds not scheduled.
116 short NumSuccsLeft; // # of succs not scheduled.
117 bool isTwoAddress : 1; // Is a two-address instruction.
118 bool isCommutable : 1; // Is a commutable instruction.
119 bool hasPhysRegDefs : 1; // Has physreg defs that are being used.
120 bool isPending : 1; // True once pending.
121 bool isAvailable : 1; // True once available.
122 bool isScheduled : 1; // True once scheduled.
123 unsigned CycleBound; // Upper/lower cycle to be scheduled at.
124 unsigned Cycle; // Once scheduled, the cycle of the op.
125 unsigned Depth; // Node depth;
126 unsigned Height; // Node height;
127 const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null.
128 const TargetRegisterClass *CopySrcRC;
130 SUnit(SDNode *node, unsigned nodenum)
131 : Node(node), OrigNode(0), NodeNum(nodenum), NodeQueueId(0), Latency(0),
132 NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
133 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
134 isPending(false), isAvailable(false), isScheduled(false),
135 CycleBound(0), Cycle(0), Depth(0), Height(0),
136 CopyDstRC(NULL), CopySrcRC(NULL) {}
138 /// addPred - This adds the specified node as a pred of the current node if
139 /// not already. This returns true if this is a new pred.
140 bool addPred(SUnit *N, bool isCtrl, bool isSpecial,
141 unsigned PhyReg = 0, int Cost = 1) {
142 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
143 if (Preds[i].Dep == N &&
144 Preds[i].isCtrl == isCtrl && Preds[i].isSpecial == isSpecial)
146 Preds.push_back(SDep(N, PhyReg, Cost, isCtrl, isSpecial));
147 N->Succs.push_back(SDep(this, PhyReg, Cost, isCtrl, isSpecial));
159 bool removePred(SUnit *N, bool isCtrl, bool isSpecial) {
160 for (SmallVector<SDep, 4>::iterator I = Preds.begin(), E = Preds.end();
162 if (I->Dep == N && I->isCtrl == isCtrl && I->isSpecial == isSpecial) {
163 bool FoundSucc = false;
164 for (SmallVector<SDep, 4>::iterator II = N->Succs.begin(),
165 EE = N->Succs.end(); II != EE; ++II)
166 if (II->Dep == this &&
167 II->isCtrl == isCtrl && II->isSpecial == isSpecial) {
172 assert(FoundSucc && "Mismatching preds / succs lists!");
187 bool isPred(SUnit *N) {
188 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
189 if (Preds[i].Dep == N)
194 bool isSucc(SUnit *N) {
195 for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i)
196 if (Succs[i].Dep == N)
201 void dump(const SelectionDAG *G) const;
202 void dumpAll(const SelectionDAG *G) const;
205 //===--------------------------------------------------------------------===//
206 /// SchedulingPriorityQueue - This interface is used to plug different
207 /// priorities computation algorithms into the list scheduler. It implements
208 /// the interface of a standard priority queue, where nodes are inserted in
209 /// arbitrary order and returned in priority order. The computation of the
210 /// priority and the representation of the queue are totally up to the
211 /// implementation to decide.
213 class SchedulingPriorityQueue {
215 virtual ~SchedulingPriorityQueue() {}
217 virtual void initNodes(DenseMap<SDNode*, SUnit*> &SUMap,
218 std::vector<SUnit> &SUnits) = 0;
219 virtual void addNode(const SUnit *SU) = 0;
220 virtual void updateNode(const SUnit *SU) = 0;
221 virtual void releaseState() = 0;
223 virtual unsigned size() const = 0;
224 virtual bool empty() const = 0;
225 virtual void push(SUnit *U) = 0;
227 virtual void push_all(const std::vector<SUnit *> &Nodes) = 0;
228 virtual SUnit *pop() = 0;
230 virtual void remove(SUnit *SU) = 0;
232 /// ScheduledNode - As each node is scheduled, this method is invoked. This
233 /// allows the priority function to adjust the priority of node that have
234 /// already been emitted.
235 virtual void ScheduledNode(SUnit *) {}
237 virtual void UnscheduledNode(SUnit *) {}
242 SelectionDAG &DAG; // DAG of the current basic block
243 MachineBasicBlock *BB; // Current basic block
244 const TargetMachine &TM; // Target processor
245 const TargetInstrInfo *TII; // Target instruction information
246 const TargetRegisterInfo *TRI; // Target processor register info
247 TargetLowering *TLI; // Target lowering info
248 MachineFunction *MF; // Machine function
249 MachineRegisterInfo &MRI; // Virtual/real register map
250 MachineConstantPool *ConstPool; // Target constant pool
251 std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s
252 // represent noop instructions.
253 DenseMap<SDNode*, SUnit*> SUnitMap; // SDNode to SUnit mapping (n -> n).
254 std::vector<SUnit> SUnits; // The scheduling units.
255 SmallSet<SDNode*, 16> CommuteSet; // Nodes that should be commuted.
257 ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb,
258 const TargetMachine &tm);
260 virtual ~ScheduleDAG() {}
262 /// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered
267 /// Run - perform scheduling.
269 MachineBasicBlock *Run();
271 /// isPassiveNode - Return true if the node is a non-scheduled leaf.
273 static bool isPassiveNode(SDNode *Node) {
274 if (isa<ConstantSDNode>(Node)) return true;
275 if (isa<ConstantFPSDNode>(Node)) return true;
276 if (isa<RegisterSDNode>(Node)) return true;
277 if (isa<GlobalAddressSDNode>(Node)) return true;
278 if (isa<BasicBlockSDNode>(Node)) return true;
279 if (isa<FrameIndexSDNode>(Node)) return true;
280 if (isa<ConstantPoolSDNode>(Node)) return true;
281 if (isa<JumpTableSDNode>(Node)) return true;
282 if (isa<ExternalSymbolSDNode>(Node)) return true;
283 if (isa<MemOperandSDNode>(Node)) return true;
284 if (Node->getOpcode() == ISD::EntryToken) return true;
288 /// NewSUnit - Creates a new SUnit and return a ptr to it.
290 SUnit *NewSUnit(SDNode *N) {
291 SUnits.push_back(SUnit(N, (unsigned)SUnits.size()));
292 SUnits.back().OrigNode = &SUnits.back();
293 return &SUnits.back();
296 /// Clone - Creates a clone of the specified SUnit. It does not copy the
297 /// predecessors / successors info nor the temporary scheduling states.
298 SUnit *Clone(SUnit *N);
300 /// BuildSchedUnits - Build SUnits from the selection dag that we are input.
301 /// This SUnit graph is similar to the SelectionDAG, but represents flagged
302 /// together nodes with a single SUnit.
303 void BuildSchedUnits();
305 /// ComputeLatency - Compute node latency.
307 void ComputeLatency(SUnit *SU);
309 /// CalculateDepths, CalculateHeights - Calculate node depth / height.
311 void CalculateDepths();
312 void CalculateHeights();
314 /// CountResults - The results of target nodes have register or immediate
315 /// operands first, then an optional chain, and optional flag operands
316 /// (which do not go into the machine instrs.)
317 static unsigned CountResults(SDNode *Node);
319 /// CountOperands - The inputs to target nodes have any actual inputs first,
320 /// followed by special operands that describe memory references, then an
321 /// optional chain operand, then flag operands. Compute the number of
322 /// actual operands that will go into the resulting MachineInstr.
323 static unsigned CountOperands(SDNode *Node);
325 /// ComputeMemOperandsEnd - Find the index one past the last
326 /// MemOperandSDNode operand
327 static unsigned ComputeMemOperandsEnd(SDNode *Node);
329 /// EmitNode - Generate machine code for an node and needed dependencies.
330 /// VRBaseMap contains, for each already emitted node, the first virtual
331 /// register number for the results of the node.
333 void EmitNode(SDNode *Node, bool IsClone,
334 DenseMap<SDOperand, unsigned> &VRBaseMap);
336 /// EmitNoop - Emit a noop instruction.
342 void dumpSchedule() const;
344 /// Schedule - Order nodes according to selected style.
346 virtual void Schedule() {}
349 /// EmitSubregNode - Generate machine code for subreg nodes.
351 void EmitSubregNode(SDNode *Node,
352 DenseMap<SDOperand, unsigned> &VRBaseMap);
354 /// getVR - Return the virtual register corresponding to the specified result
355 /// of the specified node.
356 unsigned getVR(SDOperand Op, DenseMap<SDOperand, unsigned> &VRBaseMap);
358 /// getDstOfCopyToRegUse - If the only use of the specified result number of
359 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
360 unsigned getDstOfOnlyCopyToRegUse(SDNode *Node, unsigned ResNo) const;
362 void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum,
363 const TargetInstrDesc *II,
364 DenseMap<SDOperand, unsigned> &VRBaseMap);
366 void AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO);
368 void EmitCrossRCCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap);
370 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
371 /// implicit physical register output.
372 void EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
374 DenseMap<SDOperand, unsigned> &VRBaseMap);
376 void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
377 const TargetInstrDesc &II,
378 DenseMap<SDOperand, unsigned> &VRBaseMap);
380 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
381 /// physical register has only a single copy use, then coalesced the copy
383 void EmitLiveInCopy(MachineBasicBlock *MBB,
384 MachineBasicBlock::iterator &InsertPos,
385 unsigned VirtReg, unsigned PhysReg,
386 const TargetRegisterClass *RC,
387 DenseMap<MachineInstr*, unsigned> &CopyRegMap);
389 /// EmitLiveInCopies - If this is the first basic block in the function,
390 /// and if it has live ins that need to be copied into vregs, emit the
391 /// copies into the top of the block.
392 void EmitLiveInCopies(MachineBasicBlock *MBB);
395 /// createBURRListDAGScheduler - This creates a bottom up register usage
396 /// reduction list scheduler.
397 ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS,
399 MachineBasicBlock *BB);
401 /// createTDRRListDAGScheduler - This creates a top down register usage
402 /// reduction list scheduler.
403 ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS,
405 MachineBasicBlock *BB);
407 /// createTDListDAGScheduler - This creates a top-down list scheduler with
408 /// a hazard recognizer.
409 ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS,
411 MachineBasicBlock *BB);
413 /// createDefaultScheduler - This creates an instruction scheduler appropriate
415 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
417 MachineBasicBlock *BB);
419 class SUnitIterator : public forward_iterator<SUnit, ptrdiff_t> {
423 SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {}
425 bool operator==(const SUnitIterator& x) const {
426 return Operand == x.Operand;
428 bool operator!=(const SUnitIterator& x) const { return !operator==(x); }
430 const SUnitIterator &operator=(const SUnitIterator &I) {
431 assert(I.Node == Node && "Cannot assign iterators to two different nodes!");
436 pointer operator*() const {
437 return Node->Preds[Operand].Dep;
439 pointer operator->() const { return operator*(); }
441 SUnitIterator& operator++() { // Preincrement
445 SUnitIterator operator++(int) { // Postincrement
446 SUnitIterator tmp = *this; ++*this; return tmp;
449 static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); }
450 static SUnitIterator end (SUnit *N) {
451 return SUnitIterator(N, (unsigned)N->Preds.size());
454 unsigned getOperand() const { return Operand; }
455 const SUnit *getNode() const { return Node; }
456 bool isCtrlDep() const { return Node->Preds[Operand].isCtrl; }
457 bool isSpecialDep() const { return Node->Preds[Operand].isSpecial; }
460 template <> struct GraphTraits<SUnit*> {
461 typedef SUnit NodeType;
462 typedef SUnitIterator ChildIteratorType;
463 static inline NodeType *getEntryNode(SUnit *N) { return N; }
464 static inline ChildIteratorType child_begin(NodeType *N) {
465 return SUnitIterator::begin(N);
467 static inline ChildIteratorType child_end(NodeType *N) {
468 return SUnitIterator::end(N);
472 template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> {
473 typedef std::vector<SUnit>::iterator nodes_iterator;
474 static nodes_iterator nodes_begin(ScheduleDAG *G) {
475 return G->SUnits.begin();
477 static nodes_iterator nodes_end(ScheduleDAG *G) {
478 return G->SUnits.end();