1 //===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAG class, which is used as the common
11 // base class for instruction schedulers. This encapsulates the scheduling DAG,
12 // which is shared between SelectionDAG and MachineInstr scheduling.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_SCHEDULEDAG_H
17 #define LLVM_CODEGEN_SCHEDULEDAG_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/ADT/DenseMap.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/GraphTraits.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/ADT/PointerIntPair.h"
30 class MachineConstantPool;
31 class MachineFunction;
32 class MachineRegisterInfo;
34 class TargetRegisterInfo;
37 class TargetInstrInfo;
40 class TargetRegisterClass;
41 template<class Graph> class GraphWriter;
43 /// SDep - Scheduling dependency. This represents one direction of an
44 /// edge in the scheduling DAG.
47 /// Kind - These are the different kinds of scheduling dependencies.
49 Data, ///< Regular data dependence (aka true-dependence).
50 Anti, ///< A register anti-dependedence (aka WAR).
51 Output, ///< A register output-dependence (aka WAW).
52 Order ///< Any other ordering dependency.
56 /// Dep - A pointer to the depending/depended-on SUnit, and an enum
57 /// indicating the kind of the dependency.
58 PointerIntPair<SUnit *, 2, Kind> Dep;
60 /// Contents - A union discriminated by the dependence kind.
62 /// Reg - For Data, Anti, and Output dependencies, the associated
63 /// register. For Data dependencies that don't currently have a register
64 /// assigned, this is set to zero.
67 /// Order - Additional information about Order dependencies.
69 /// isNormalMemory - True if both sides of the dependence
70 /// access memory in non-volatile and fully modeled ways.
71 bool isNormalMemory : 1;
73 /// isMustAlias - True if both sides of the dependence are known to
74 /// access the same memory.
77 /// isArtificial - True if this is an artificial dependency, meaning
78 /// it is not necessary for program correctness, and may be safely
79 /// deleted if necessary.
80 bool isArtificial : 1;
84 /// Latency - The time associated with this edge. Often this is just
85 /// the value of the Latency field of the predecessor, however advanced
86 /// models may provide additional information about specific edges.
90 /// SDep - Construct a null SDep. This is only for use by container
91 /// classes which require default constructors. SUnits may not
92 /// have null SDep edges.
93 SDep() : Dep(0, Data) {}
95 /// SDep - Construct an SDep with the specified values.
96 SDep(SUnit *S, Kind kind, unsigned latency = 1, unsigned Reg = 0,
97 bool isNormalMemory = false, bool isMustAlias = false,
98 bool isArtificial = false)
99 : Dep(S, kind), Contents(), Latency(latency) {
104 "SDep::Anti and SDep::Output must use a non-zero Reg!");
107 assert(!isMustAlias && "isMustAlias only applies with SDep::Order!");
108 assert(!isArtificial && "isArtificial only applies with SDep::Order!");
112 assert(Reg == 0 && "Reg given for non-register dependence!");
113 Contents.Order.isNormalMemory = isNormalMemory;
114 Contents.Order.isMustAlias = isMustAlias;
115 Contents.Order.isArtificial = isArtificial;
120 bool operator==(const SDep &Other) const {
121 if (Dep != Other.Dep || Latency != Other.Latency) return false;
122 switch (Dep.getInt()) {
126 return Contents.Reg == Other.Contents.Reg;
128 return Contents.Order.isNormalMemory ==
129 Other.Contents.Order.isNormalMemory &&
130 Contents.Order.isMustAlias == Other.Contents.Order.isMustAlias &&
131 Contents.Order.isArtificial == Other.Contents.Order.isArtificial;
133 llvm_unreachable("Invalid dependency kind!");
136 bool operator!=(const SDep &Other) const {
137 return !operator==(Other);
140 /// getLatency - Return the latency value for this edge, which roughly
141 /// means the minimum number of cycles that must elapse between the
142 /// predecessor and the successor, given that they have this edge
144 unsigned getLatency() const {
148 /// setLatency - Set the latency for this edge.
149 void setLatency(unsigned Lat) {
153 //// getSUnit - Return the SUnit to which this edge points.
154 SUnit *getSUnit() const {
155 return Dep.getPointer();
158 //// setSUnit - Assign the SUnit to which this edge points.
159 void setSUnit(SUnit *SU) {
163 /// getKind - Return an enum value representing the kind of the dependence.
164 Kind getKind() const {
168 /// isCtrl - Shorthand for getKind() != SDep::Data.
169 bool isCtrl() const {
170 return getKind() != Data;
173 /// isNormalMemory - Test if this is an Order dependence between two
174 /// memory accesses where both sides of the dependence access memory
175 /// in non-volatile and fully modeled ways.
176 bool isNormalMemory() const {
177 return getKind() == Order && Contents.Order.isNormalMemory;
180 /// isMustAlias - Test if this is an Order dependence that is marked
181 /// as "must alias", meaning that the SUnits at either end of the edge
182 /// have a memory dependence on a known memory location.
183 bool isMustAlias() const {
184 return getKind() == Order && Contents.Order.isMustAlias;
187 /// isArtificial - Test if this is an Order dependence that is marked
188 /// as "artificial", meaning it isn't necessary for correctness.
189 bool isArtificial() const {
190 return getKind() == Order && Contents.Order.isArtificial;
193 /// isAssignedRegDep - Test if this is a Data dependence that is
194 /// associated with a register.
195 bool isAssignedRegDep() const {
196 return getKind() == Data && Contents.Reg != 0;
199 /// getReg - Return the register associated with this edge. This is
200 /// only valid on Data, Anti, and Output edges. On Data edges, this
201 /// value may be zero, meaning there is no associated register.
202 unsigned getReg() const {
203 assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
204 "getReg called on non-register dependence edge!");
208 /// setReg - Assign the associated register for this edge. This is
209 /// only valid on Data, Anti, and Output edges. On Anti and Output
210 /// edges, this value must not be zero. On Data edges, the value may
211 /// be zero, which would mean that no specific register is associated
213 void setReg(unsigned Reg) {
214 assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
215 "setReg called on non-register dependence edge!");
216 assert((getKind() != Anti || Reg != 0) &&
217 "SDep::Anti edge cannot use the zero register!");
218 assert((getKind() != Output || Reg != 0) &&
219 "SDep::Output edge cannot use the zero register!");
225 struct isPodLike<SDep> { static const bool value = true; };
227 /// SUnit - Scheduling unit. This is a node in the scheduling DAG.
230 SDNode *Node; // Representative node.
231 MachineInstr *Instr; // Alternatively, a MachineInstr.
233 SUnit *OrigNode; // If not this, the node from which
234 // this node was cloned.
235 // (SD scheduling only)
237 // Preds/Succs - The SUnits before/after us in the graph.
238 SmallVector<SDep, 4> Preds; // All sunit predecessors.
239 SmallVector<SDep, 4> Succs; // All sunit successors.
241 typedef SmallVector<SDep, 4>::iterator pred_iterator;
242 typedef SmallVector<SDep, 4>::iterator succ_iterator;
243 typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator;
244 typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator;
246 unsigned NodeNum; // Entry # of node in the node vector.
247 unsigned NodeQueueId; // Queue id of node.
248 unsigned NumPreds; // # of SDep::Data preds.
249 unsigned NumSuccs; // # of SDep::Data sucss.
250 unsigned NumPredsLeft; // # of preds not scheduled.
251 unsigned NumSuccsLeft; // # of succs not scheduled.
252 unsigned short NumRegDefsLeft; // # of reg defs with no scheduled use.
253 unsigned short Latency; // Node latency.
254 bool isVRegCycle : 1; // May use and def the same vreg.
255 bool isCall : 1; // Is a function call.
256 bool isCallOp : 1; // Is a function call operand.
257 bool isTwoAddress : 1; // Is a two-address instruction.
258 bool isCommutable : 1; // Is a commutable instruction.
259 bool hasPhysRegDefs : 1; // Has physreg defs that are being used.
260 bool hasPhysRegClobbers : 1; // Has any physreg defs, used or not.
261 bool isPending : 1; // True once pending.
262 bool isAvailable : 1; // True once available.
263 bool isScheduled : 1; // True once scheduled.
264 bool isScheduleHigh : 1; // True if preferable to schedule high.
265 bool isScheduleLow : 1; // True if preferable to schedule low.
266 bool isCloned : 1; // True if this node has been cloned.
267 Sched::Preference SchedulingPref; // Scheduling preference.
270 bool isDepthCurrent : 1; // True if Depth is current.
271 bool isHeightCurrent : 1; // True if Height is current.
272 unsigned Depth; // Node depth.
273 unsigned Height; // Node height.
275 const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null.
276 const TargetRegisterClass *CopySrcRC;
278 /// SUnit - Construct an SUnit for pre-regalloc scheduling to represent
279 /// an SDNode and any nodes flagged to it.
280 SUnit(SDNode *node, unsigned nodenum)
281 : Node(node), Instr(0), OrigNode(0), NodeNum(nodenum),
282 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
283 NumSuccsLeft(0), NumRegDefsLeft(0), Latency(0),
284 isVRegCycle(false), isCall(false), isCallOp(false), isTwoAddress(false),
285 isCommutable(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
286 isPending(false), isAvailable(false), isScheduled(false),
287 isScheduleHigh(false), isScheduleLow(false), isCloned(false),
288 SchedulingPref(Sched::None),
289 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
290 CopyDstRC(NULL), CopySrcRC(NULL) {}
292 /// SUnit - Construct an SUnit for post-regalloc scheduling to represent
294 SUnit(MachineInstr *instr, unsigned nodenum)
295 : Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum),
296 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
297 NumSuccsLeft(0), NumRegDefsLeft(0), Latency(0),
298 isVRegCycle(false), isCall(false), isCallOp(false), isTwoAddress(false),
299 isCommutable(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
300 isPending(false), isAvailable(false), isScheduled(false),
301 isScheduleHigh(false), isScheduleLow(false), isCloned(false),
302 SchedulingPref(Sched::None),
303 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
304 CopyDstRC(NULL), CopySrcRC(NULL) {}
306 /// SUnit - Construct a placeholder SUnit.
308 : Node(0), Instr(0), OrigNode(0), NodeNum(~0u),
309 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
310 NumSuccsLeft(0), NumRegDefsLeft(0), Latency(0),
311 isVRegCycle(false), isCall(false), isCallOp(false), isTwoAddress(false),
312 isCommutable(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
313 isPending(false), isAvailable(false), isScheduled(false),
314 isScheduleHigh(false), isScheduleLow(false), isCloned(false),
315 SchedulingPref(Sched::None),
316 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
317 CopyDstRC(NULL), CopySrcRC(NULL) {}
319 /// setNode - Assign the representative SDNode for this SUnit.
320 /// This may be used during pre-regalloc scheduling.
321 void setNode(SDNode *N) {
322 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!");
326 /// getNode - Return the representative SDNode for this SUnit.
327 /// This may be used during pre-regalloc scheduling.
328 SDNode *getNode() const {
329 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!");
333 /// isInstr - Return true if this SUnit refers to a machine instruction as
334 /// opposed to an SDNode.
335 bool isInstr() const { return Instr; }
337 /// setInstr - Assign the instruction for the SUnit.
338 /// This may be used during post-regalloc scheduling.
339 void setInstr(MachineInstr *MI) {
340 assert(!Node && "Setting MachineInstr of SUnit with SDNode!");
344 /// getInstr - Return the representative MachineInstr for this SUnit.
345 /// This may be used during post-regalloc scheduling.
346 MachineInstr *getInstr() const {
347 assert(!Node && "Reading MachineInstr of SUnit with SDNode!");
351 /// addPred - This adds the specified edge as a pred of the current node if
352 /// not already. It also adds the current node as a successor of the
354 bool addPred(const SDep &D);
356 /// removePred - This removes the specified edge as a pred of the current
357 /// node if it exists. It also removes the current node as a successor of
358 /// the specified node.
359 void removePred(const SDep &D);
361 /// getDepth - Return the depth of this node, which is the length of the
362 /// maximum path up to any node which has no predecessors.
363 unsigned getDepth() const {
365 const_cast<SUnit *>(this)->ComputeDepth();
369 /// getHeight - Return the height of this node, which is the length of the
370 /// maximum path down to any node which has no successors.
371 unsigned getHeight() const {
372 if (!isHeightCurrent)
373 const_cast<SUnit *>(this)->ComputeHeight();
377 /// setDepthToAtLeast - If NewDepth is greater than this node's
378 /// depth value, set it to be the new depth value. This also
379 /// recursively marks successor nodes dirty.
380 void setDepthToAtLeast(unsigned NewDepth);
382 /// setDepthToAtLeast - If NewDepth is greater than this node's
383 /// depth value, set it to be the new height value. This also
384 /// recursively marks predecessor nodes dirty.
385 void setHeightToAtLeast(unsigned NewHeight);
387 /// setDepthDirty - Set a flag in this node to indicate that its
388 /// stored Depth value will require recomputation the next time
389 /// getDepth() is called.
390 void setDepthDirty();
392 /// setHeightDirty - Set a flag in this node to indicate that its
393 /// stored Height value will require recomputation the next time
394 /// getHeight() is called.
395 void setHeightDirty();
397 /// isPred - Test if node N is a predecessor of this node.
398 bool isPred(SUnit *N) {
399 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
400 if (Preds[i].getSUnit() == N)
405 /// isSucc - Test if node N is a successor of this node.
406 bool isSucc(SUnit *N) {
407 for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i)
408 if (Succs[i].getSUnit() == N)
413 void dump(const ScheduleDAG *G) const;
414 void dumpAll(const ScheduleDAG *G) const;
415 void print(raw_ostream &O, const ScheduleDAG *G) const;
419 void ComputeHeight();
422 //===--------------------------------------------------------------------===//
423 /// SchedulingPriorityQueue - This interface is used to plug different
424 /// priorities computation algorithms into the list scheduler. It implements
425 /// the interface of a standard priority queue, where nodes are inserted in
426 /// arbitrary order and returned in priority order. The computation of the
427 /// priority and the representation of the queue are totally up to the
428 /// implementation to decide.
430 class SchedulingPriorityQueue {
431 virtual void anchor();
435 SchedulingPriorityQueue(bool rf = false):
436 CurCycle(0), HasReadyFilter(rf) {}
437 virtual ~SchedulingPriorityQueue() {}
439 virtual bool isBottomUp() const = 0;
441 virtual void initNodes(std::vector<SUnit> &SUnits) = 0;
442 virtual void addNode(const SUnit *SU) = 0;
443 virtual void updateNode(const SUnit *SU) = 0;
444 virtual void releaseState() = 0;
446 virtual bool empty() const = 0;
448 bool hasReadyFilter() const { return HasReadyFilter; }
450 virtual bool tracksRegPressure() const { return false; }
452 virtual bool isReady(SUnit *) const {
453 assert(!HasReadyFilter && "The ready filter must override isReady()");
456 virtual void push(SUnit *U) = 0;
458 void push_all(const std::vector<SUnit *> &Nodes) {
459 for (std::vector<SUnit *>::const_iterator I = Nodes.begin(),
460 E = Nodes.end(); I != E; ++I)
464 virtual SUnit *pop() = 0;
466 virtual void remove(SUnit *SU) = 0;
468 virtual void dump(ScheduleDAG *) const {}
470 /// ScheduledNode - As each node is scheduled, this method is invoked. This
471 /// allows the priority function to adjust the priority of related
472 /// unscheduled nodes, for example.
474 virtual void ScheduledNode(SUnit *) {}
476 virtual void UnscheduledNode(SUnit *) {}
478 void setCurCycle(unsigned Cycle) {
482 unsigned getCurCycle() const {
489 MachineBasicBlock *BB; // The block in which to insert instructions
490 MachineBasicBlock::iterator InsertPos;// The position to insert instructions
491 const TargetMachine &TM; // Target processor
492 const TargetInstrInfo *TII; // Target instruction information
493 const TargetRegisterInfo *TRI; // Target processor register info
494 MachineFunction &MF; // Machine function
495 MachineRegisterInfo &MRI; // Virtual/real register map
496 std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s
497 // represent noop instructions.
498 std::vector<SUnit> SUnits; // The scheduling units.
499 SUnit EntrySU; // Special node for the region entry.
500 SUnit ExitSU; // Special node for the region exit.
503 static const bool StressSched = false;
508 explicit ScheduleDAG(MachineFunction &mf);
510 virtual ~ScheduleDAG();
512 /// getInstrDesc - Return the MCInstrDesc of this SUnit.
513 /// Return NULL for SDNodes without a machine opcode.
514 const MCInstrDesc *getInstrDesc(const SUnit *SU) const {
515 if (SU->isInstr()) return &SU->getInstr()->getDesc();
516 return getNodeDesc(SU->getNode());
519 /// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered
522 void viewGraph(const Twine &Name, const Twine &Title);
525 /// EmitSchedule - Insert MachineInstrs into the MachineBasicBlock
526 /// according to the order specified in Sequence.
528 virtual MachineBasicBlock *EmitSchedule() = 0;
530 void dumpSchedule() const;
532 virtual void dumpNode(const SUnit *SU) const = 0;
534 /// getGraphNodeLabel - Return a label for an SUnit node in a visualization
535 /// of the ScheduleDAG.
536 virtual std::string getGraphNodeLabel(const SUnit *SU) const = 0;
538 /// getDAGLabel - Return a label for the region of code covered by the DAG.
539 virtual std::string getDAGName() const = 0;
541 /// addCustomGraphFeatures - Add custom features for a visualization of
543 virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {}
546 /// VerifyScheduledDAG - Verify that all SUnits were scheduled and that
547 /// their state is consistent. Return the number of scheduled SUnits.
548 unsigned VerifyScheduledDAG(bool isBottomUp);
552 /// Run - perform scheduling.
554 void Run(MachineBasicBlock *bb, MachineBasicBlock::iterator insertPos);
556 /// ComputeLatency - Compute node latency.
558 virtual void ComputeLatency(SUnit *SU) = 0;
560 /// ComputeOperandLatency - Override dependence edge latency using
561 /// operand use/def information
563 virtual void ComputeOperandLatency(SUnit *, SUnit *,
566 /// Schedule - Order nodes according to selected style, filling
567 /// in the Sequence member.
569 virtual void Schedule() = 0;
571 /// ForceUnitLatencies - Return true if all scheduling edges should be given
572 /// a latency value of one. The default is to return false; schedulers may
573 /// override this as needed.
574 virtual bool ForceUnitLatencies() const { return false; }
576 /// EmitNoop - Emit a noop instruction.
580 void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap);
583 // Return the MCInstrDesc of this SDNode or NULL.
584 const MCInstrDesc *getNodeDesc(const SDNode *Node) const;
587 class SUnitIterator : public std::iterator<std::forward_iterator_tag,
592 SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {}
594 bool operator==(const SUnitIterator& x) const {
595 return Operand == x.Operand;
597 bool operator!=(const SUnitIterator& x) const { return !operator==(x); }
599 const SUnitIterator &operator=(const SUnitIterator &I) {
600 assert(I.Node==Node && "Cannot assign iterators to two different nodes!");
605 pointer operator*() const {
606 return Node->Preds[Operand].getSUnit();
608 pointer operator->() const { return operator*(); }
610 SUnitIterator& operator++() { // Preincrement
614 SUnitIterator operator++(int) { // Postincrement
615 SUnitIterator tmp = *this; ++*this; return tmp;
618 static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); }
619 static SUnitIterator end (SUnit *N) {
620 return SUnitIterator(N, (unsigned)N->Preds.size());
623 unsigned getOperand() const { return Operand; }
624 const SUnit *getNode() const { return Node; }
625 /// isCtrlDep - Test if this is not an SDep::Data dependence.
626 bool isCtrlDep() const {
627 return getSDep().isCtrl();
629 bool isArtificialDep() const {
630 return getSDep().isArtificial();
632 const SDep &getSDep() const {
633 return Node->Preds[Operand];
637 template <> struct GraphTraits<SUnit*> {
638 typedef SUnit NodeType;
639 typedef SUnitIterator ChildIteratorType;
640 static inline NodeType *getEntryNode(SUnit *N) { return N; }
641 static inline ChildIteratorType child_begin(NodeType *N) {
642 return SUnitIterator::begin(N);
644 static inline ChildIteratorType child_end(NodeType *N) {
645 return SUnitIterator::end(N);
649 template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> {
650 typedef std::vector<SUnit>::iterator nodes_iterator;
651 static nodes_iterator nodes_begin(ScheduleDAG *G) {
652 return G->SUnits.begin();
654 static nodes_iterator nodes_end(ScheduleDAG *G) {
655 return G->SUnits.end();
659 /// ScheduleDAGTopologicalSort is a class that computes a topological
660 /// ordering for SUnits and provides methods for dynamically updating
661 /// the ordering as new edges are added.
663 /// This allows a very fast implementation of IsReachable, for example.
665 class ScheduleDAGTopologicalSort {
666 /// SUnits - A reference to the ScheduleDAG's SUnits.
667 std::vector<SUnit> &SUnits;
669 /// Index2Node - Maps topological index to the node number.
670 std::vector<int> Index2Node;
671 /// Node2Index - Maps the node number to its topological index.
672 std::vector<int> Node2Index;
673 /// Visited - a set of nodes visited during a DFS traversal.
676 /// DFS - make a DFS traversal and mark all nodes affected by the
677 /// edge insertion. These nodes will later get new topological indexes
678 /// by means of the Shift method.
679 void DFS(const SUnit *SU, int UpperBound, bool& HasLoop);
681 /// Shift - reassign topological indexes for the nodes in the DAG
682 /// to preserve the topological ordering.
683 void Shift(BitVector& Visited, int LowerBound, int UpperBound);
685 /// Allocate - assign the topological index to the node n.
686 void Allocate(int n, int index);
689 explicit ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits);
691 /// InitDAGTopologicalSorting - create the initial topological
692 /// ordering from the DAG to be scheduled.
693 void InitDAGTopologicalSorting();
695 /// IsReachable - Checks if SU is reachable from TargetSU.
696 bool IsReachable(const SUnit *SU, const SUnit *TargetSU);
698 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU
699 /// will create a cycle.
700 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU);
702 /// AddPred - Updates the topological ordering to accommodate an edge
703 /// to be added from SUnit X to SUnit Y.
704 void AddPred(SUnit *Y, SUnit *X);
706 /// RemovePred - Updates the topological ordering to accommodate an
707 /// an edge to be removed from the specified node N from the predecessors
708 /// of the current node M.
709 void RemovePred(SUnit *M, SUnit *N);
711 typedef std::vector<int>::iterator iterator;
712 typedef std::vector<int>::const_iterator const_iterator;
713 iterator begin() { return Index2Node.begin(); }
714 const_iterator begin() const { return Index2Node.begin(); }
715 iterator end() { return Index2Node.end(); }
716 const_iterator end() const { return Index2Node.end(); }
718 typedef std::vector<int>::reverse_iterator reverse_iterator;
719 typedef std::vector<int>::const_reverse_iterator const_reverse_iterator;
720 reverse_iterator rbegin() { return Index2Node.rbegin(); }
721 const_reverse_iterator rbegin() const { return Index2Node.rbegin(); }
722 reverse_iterator rend() { return Index2Node.rend(); }
723 const_reverse_iterator rend() const { return Index2Node.rend(); }