1 //===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAG class, which is used as the common
11 // base class for instruction schedulers.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SCHEDULEDAG_H
16 #define LLVM_CODEGEN_SCHEDULEDAG_H
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/GraphTraits.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/PointerIntPair.h"
27 class MachineConstantPool;
28 class MachineFunction;
29 class MachineModuleInfo;
30 class MachineRegisterInfo;
32 class TargetRegisterInfo;
36 class TargetInstrInfo;
37 class TargetInstrDesc;
40 class TargetRegisterClass;
41 template<class Graph> class GraphWriter;
43 /// SDep - Scheduling dependency. This represents one direction of an
44 /// edge in the scheduling DAG.
47 /// Kind - These are the different kinds of scheduling dependencies.
49 Data, ///< Regular data dependence (aka true-dependence).
50 Anti, ///< A register anti-dependedence (aka WAR).
51 Output, ///< A register output-dependence (aka WAW).
52 Order ///< Any other ordering dependency.
56 /// Dep - A pointer to the depending/depended-on SUnit, and an enum
57 /// indicating the kind of the dependency.
58 PointerIntPair<SUnit *, 2, Kind> Dep;
60 /// Contents - A union discriminated by the dependence kind.
62 /// Reg - For Data, Anti, and Output dependencies, the associated
63 /// register. For Data dependencies that don't currently have a register
64 /// assigned, this is set to zero.
67 /// Order - Additional information about Order dependencies.
69 /// isNormalMemory - True if both sides of the dependence
70 /// access memory in non-volatile and fully modeled ways.
71 bool isNormalMemory : 1;
73 /// isMustAlias - True if both sides of the dependence are known to
74 /// access the same memory.
77 /// isArtificial - True if this is an artificial dependency, meaning
78 /// it is not necessary for program correctness, and may be safely
79 /// deleted if necessary.
80 bool isArtificial : 1;
84 /// Latency - The time associated with this edge. Often this is just
85 /// the value of the Latency field of the predecessor, however advanced
86 /// models may provide additional information about specific edges.
90 /// SDep - Construct a null SDep. This is only for use by container
91 /// classes which require default constructors. SUnits may not
92 /// have null SDep edges.
93 SDep() : Dep(0, Data) {}
95 /// SDep - Construct an SDep with the specified values.
96 SDep(SUnit *S, Kind kind, unsigned latency = 1, unsigned Reg = 0,
97 bool isNormalMemory = false, bool isMustAlias = false,
98 bool isArtificial = false)
99 : Dep(S, kind), Contents(), Latency(latency) {
104 "SDep::Anti and SDep::Output must use a non-zero Reg!");
107 assert(!isMustAlias && "isMustAlias only applies with SDep::Order!");
108 assert(!isArtificial && "isArtificial only applies with SDep::Order!");
112 assert(Reg == 0 && "Reg given for non-register dependence!");
113 Contents.Order.isNormalMemory = isNormalMemory;
114 Contents.Order.isMustAlias = isMustAlias;
115 Contents.Order.isArtificial = isArtificial;
120 bool operator==(const SDep &Other) const {
121 if (Dep != Other.Dep || Latency != Other.Latency) return false;
122 switch (Dep.getInt()) {
126 return Contents.Reg == Other.Contents.Reg;
128 return Contents.Order.isNormalMemory ==
129 Other.Contents.Order.isNormalMemory &&
130 Contents.Order.isMustAlias == Other.Contents.Order.isMustAlias &&
131 Contents.Order.isArtificial == Other.Contents.Order.isArtificial;
133 assert(0 && "Invalid dependency kind!");
137 bool operator!=(const SDep &Other) const {
138 return !operator==(Other);
141 /// getLatency - Return the latency value for this edge, which roughly
142 /// means the minimum number of cycles that must elapse between the
143 /// predecessor and the successor, given that they have this edge
145 unsigned getLatency() const {
149 //// getSUnit - Return the SUnit to which this edge points.
150 SUnit *getSUnit() const {
151 return Dep.getPointer();
154 //// setSUnit - Assign the SUnit to which this edge points.
155 void setSUnit(SUnit *SU) {
159 /// getKind - Return an enum value representing the kind of the dependence.
160 Kind getKind() const {
164 /// isCtrl - Shorthand for getKind() != SDep::Data.
165 bool isCtrl() const {
166 return getKind() != Data;
169 /// isMustAlias - Test if this is an Order dependence that is marked
170 /// as "must alias", meaning that the SUnits at either end of the edge
171 /// have a memory dependence on a known memory location.
172 bool isMustAlias() const {
173 return getKind() == Order && Contents.Order.isMustAlias;
176 /// isArtificial - Test if this is an Order dependence that is marked
177 /// as "artificial", meaning it isn't necessary for correctness.
178 bool isArtificial() const {
179 return getKind() == Order && Contents.Order.isArtificial;
182 /// isAssignedRegDep - Test if this is a Data dependence that is
183 /// associated with a register.
184 bool isAssignedRegDep() const {
185 return getKind() == Data && Contents.Reg != 0;
188 /// getReg - Return the register associated with this edge. This is
189 /// only valid on Data, Anti, and Output edges. On Data edges, this
190 /// value may be zero, meaning there is no associated register.
191 unsigned getReg() const {
192 assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
193 "getReg called on non-register dependence edge!");
197 /// setReg - Assign the associated register for this edge. This is
198 /// only valid on Data, Anti, and Output edges. On Anti and Output
199 /// edges, this value must not be zero. On Data edges, the value may
200 /// be zero, which would mean that no specific register is associated
202 void setReg(unsigned Reg) {
203 assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
204 "setReg called on non-register dependence edge!");
205 assert((getKind() != Anti || Reg != 0) &&
206 "SDep::Anti edge cannot use the zero register!");
207 assert((getKind() != Output || Reg != 0) &&
208 "SDep::Output edge cannot use the zero register!");
213 /// SUnit - Scheduling unit. This is a node in the scheduling DAG.
216 SDNode *Node; // Representative node.
217 MachineInstr *Instr; // Alternatively, a MachineInstr.
219 SUnit *OrigNode; // If not this, the node from which
220 // this node was cloned.
222 // Preds/Succs - The SUnits before/after us in the graph. The boolean value
223 // is true if the edge is a token chain edge, false if it is a value edge.
224 SmallVector<SDep, 4> Preds; // All sunit predecessors.
225 SmallVector<SDep, 4> Succs; // All sunit successors.
227 typedef SmallVector<SDep, 4>::iterator pred_iterator;
228 typedef SmallVector<SDep, 4>::iterator succ_iterator;
229 typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator;
230 typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator;
232 unsigned NodeNum; // Entry # of node in the node vector.
233 unsigned NodeQueueId; // Queue id of node.
234 unsigned short Latency; // Node latency.
235 short NumPreds; // # of SDep::Data preds.
236 short NumSuccs; // # of SDep::Data sucss.
237 short NumPredsLeft; // # of preds not scheduled.
238 short NumSuccsLeft; // # of succs not scheduled.
239 bool isTwoAddress : 1; // Is a two-address instruction.
240 bool isCommutable : 1; // Is a commutable instruction.
241 bool hasPhysRegDefs : 1; // Has physreg defs that are being used.
242 bool isPending : 1; // True once pending.
243 bool isAvailable : 1; // True once available.
244 bool isScheduled : 1; // True once scheduled.
245 unsigned CycleBound; // Upper/lower cycle to be scheduled at.
246 unsigned Cycle; // Once scheduled, the cycle of the op.
247 unsigned Depth; // Node depth;
248 unsigned Height; // Node height;
249 const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null.
250 const TargetRegisterClass *CopySrcRC;
252 /// SUnit - Construct an SUnit for pre-regalloc scheduling to represent
253 /// an SDNode and any nodes flagged to it.
254 SUnit(SDNode *node, unsigned nodenum)
255 : Node(node), Instr(0), OrigNode(0), NodeNum(nodenum), NodeQueueId(0),
256 Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
257 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
258 isPending(false), isAvailable(false), isScheduled(false),
259 CycleBound(0), Cycle(~0u), Depth(0), Height(0),
260 CopyDstRC(NULL), CopySrcRC(NULL) {}
262 /// SUnit - Construct an SUnit for post-regalloc scheduling to represent
264 SUnit(MachineInstr *instr, unsigned nodenum)
265 : Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum), NodeQueueId(0),
266 Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
267 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
268 isPending(false), isAvailable(false), isScheduled(false),
269 CycleBound(0), Cycle(~0u), Depth(0), Height(0),
270 CopyDstRC(NULL), CopySrcRC(NULL) {}
272 /// setNode - Assign the representative SDNode for this SUnit.
273 /// This may be used during pre-regalloc scheduling.
274 void setNode(SDNode *N) {
275 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!");
279 /// getNode - Return the representative SDNode for this SUnit.
280 /// This may be used during pre-regalloc scheduling.
281 SDNode *getNode() const {
282 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!");
286 /// setInstr - Assign the instruction for the SUnit.
287 /// This may be used during post-regalloc scheduling.
288 void setInstr(MachineInstr *MI) {
289 assert(!Node && "Setting MachineInstr of SUnit with SDNode!");
293 /// getInstr - Return the representative MachineInstr for this SUnit.
294 /// This may be used during post-regalloc scheduling.
295 MachineInstr *getInstr() const {
296 assert(!Node && "Reading MachineInstr of SUnit with SDNode!");
300 /// addPred - This adds the specified edge as a pred of the current node if
301 /// not already. It also adds the current node as a successor of the
303 void addPred(const SDep &D);
305 /// removePred - This removes the specified edge as a pred of the current
306 /// node if it exists. It also removes the current node as a successor of
307 /// the specified node.
308 void removePred(const SDep &D);
310 bool isPred(SUnit *N) {
311 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
312 if (Preds[i].getSUnit() == N)
317 bool isSucc(SUnit *N) {
318 for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i)
319 if (Succs[i].getSUnit() == N)
324 void dump(const ScheduleDAG *G) const;
325 void dumpAll(const ScheduleDAG *G) const;
326 void print(raw_ostream &O, const ScheduleDAG *G) const;
329 //===--------------------------------------------------------------------===//
330 /// SchedulingPriorityQueue - This interface is used to plug different
331 /// priorities computation algorithms into the list scheduler. It implements
332 /// the interface of a standard priority queue, where nodes are inserted in
333 /// arbitrary order and returned in priority order. The computation of the
334 /// priority and the representation of the queue are totally up to the
335 /// implementation to decide.
337 class SchedulingPriorityQueue {
339 virtual ~SchedulingPriorityQueue() {}
341 virtual void initNodes(std::vector<SUnit> &SUnits) = 0;
342 virtual void addNode(const SUnit *SU) = 0;
343 virtual void updateNode(const SUnit *SU) = 0;
344 virtual void releaseState() = 0;
346 virtual unsigned size() const = 0;
347 virtual bool empty() const = 0;
348 virtual void push(SUnit *U) = 0;
350 virtual void push_all(const std::vector<SUnit *> &Nodes) = 0;
351 virtual SUnit *pop() = 0;
353 virtual void remove(SUnit *SU) = 0;
355 /// ScheduledNode - As each node is scheduled, this method is invoked. This
356 /// allows the priority function to adjust the priority of related
357 /// unscheduled nodes, for example.
359 virtual void ScheduledNode(SUnit *) {}
361 virtual void UnscheduledNode(SUnit *) {}
366 SelectionDAG *DAG; // DAG of the current basic block
367 MachineBasicBlock *BB; // Current basic block
368 const TargetMachine &TM; // Target processor
369 const TargetInstrInfo *TII; // Target instruction information
370 const TargetRegisterInfo *TRI; // Target processor register info
371 TargetLowering *TLI; // Target lowering info
372 MachineFunction *MF; // Machine function
373 MachineRegisterInfo &MRI; // Virtual/real register map
374 MachineConstantPool *ConstPool; // Target constant pool
375 std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s
376 // represent noop instructions.
377 std::vector<SUnit> SUnits; // The scheduling units.
379 ScheduleDAG(SelectionDAG *dag, MachineBasicBlock *bb,
380 const TargetMachine &tm);
382 virtual ~ScheduleDAG();
384 /// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered
389 /// Run - perform scheduling.
393 /// BuildSchedUnits - Build SUnits and set up their Preds and Succs
394 /// to form the scheduling dependency graph.
396 virtual void BuildSchedUnits() = 0;
398 /// ComputeLatency - Compute node latency.
400 virtual void ComputeLatency(SUnit *SU) { SU->Latency = 1; }
402 /// CalculateDepths, CalculateHeights - Calculate node depth / height.
404 void CalculateDepths();
405 void CalculateHeights();
408 /// EmitNoop - Emit a noop instruction.
413 virtual MachineBasicBlock *EmitSchedule() = 0;
415 void dumpSchedule() const;
417 /// Schedule - Order nodes according to selected style, filling
418 /// in the Sequence member.
420 virtual void Schedule() = 0;
422 virtual void dumpNode(const SUnit *SU) const = 0;
424 /// getGraphNodeLabel - Return a label for an SUnit node in a visualization
425 /// of the ScheduleDAG.
426 virtual std::string getGraphNodeLabel(const SUnit *SU) const = 0;
428 /// addCustomGraphFeatures - Add custom features for a visualization of
430 virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {}
433 /// VerifySchedule - Verify that all SUnits were scheduled and that
434 /// their state is consistent.
435 void VerifySchedule(bool isBottomUp);
439 void AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO);
441 void EmitCrossRCCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap);
444 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
445 /// physical register has only a single copy use, then coalesced the copy
447 void EmitLiveInCopy(MachineBasicBlock *MBB,
448 MachineBasicBlock::iterator &InsertPos,
449 unsigned VirtReg, unsigned PhysReg,
450 const TargetRegisterClass *RC,
451 DenseMap<MachineInstr*, unsigned> &CopyRegMap);
453 /// EmitLiveInCopies - If this is the first basic block in the function,
454 /// and if it has live ins that need to be copied into vregs, emit the
455 /// copies into the top of the block.
456 void EmitLiveInCopies(MachineBasicBlock *MBB);
459 class SUnitIterator : public forward_iterator<SUnit, ptrdiff_t> {
463 SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {}
465 bool operator==(const SUnitIterator& x) const {
466 return Operand == x.Operand;
468 bool operator!=(const SUnitIterator& x) const { return !operator==(x); }
470 const SUnitIterator &operator=(const SUnitIterator &I) {
471 assert(I.Node == Node && "Cannot assign iterators to two different nodes!");
476 pointer operator*() const {
477 return Node->Preds[Operand].getSUnit();
479 pointer operator->() const { return operator*(); }
481 SUnitIterator& operator++() { // Preincrement
485 SUnitIterator operator++(int) { // Postincrement
486 SUnitIterator tmp = *this; ++*this; return tmp;
489 static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); }
490 static SUnitIterator end (SUnit *N) {
491 return SUnitIterator(N, (unsigned)N->Preds.size());
494 unsigned getOperand() const { return Operand; }
495 const SUnit *getNode() const { return Node; }
496 /// isCtrlDep - Test if this is not an SDep::Data dependence.
497 bool isCtrlDep() const {
498 return getSDep().isCtrl();
500 bool isArtificialDep() const {
501 return getSDep().isArtificial();
503 const SDep &getSDep() const {
504 return Node->Preds[Operand];
508 template <> struct GraphTraits<SUnit*> {
509 typedef SUnit NodeType;
510 typedef SUnitIterator ChildIteratorType;
511 static inline NodeType *getEntryNode(SUnit *N) { return N; }
512 static inline ChildIteratorType child_begin(NodeType *N) {
513 return SUnitIterator::begin(N);
515 static inline ChildIteratorType child_end(NodeType *N) {
516 return SUnitIterator::end(N);
520 template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> {
521 typedef std::vector<SUnit>::iterator nodes_iterator;
522 static nodes_iterator nodes_begin(ScheduleDAG *G) {
523 return G->SUnits.begin();
525 static nodes_iterator nodes_end(ScheduleDAG *G) {
526 return G->SUnits.end();
530 /// ScheduleDAGTopologicalSort is a class that computes a topological
531 /// ordering for SUnits and provides methods for dynamically updating
532 /// the ordering as new edges are added.
534 /// This allows a very fast implementation of IsReachable, for example.
536 class ScheduleDAGTopologicalSort {
537 /// SUnits - A reference to the ScheduleDAG's SUnits.
538 std::vector<SUnit> &SUnits;
540 /// Index2Node - Maps topological index to the node number.
541 std::vector<int> Index2Node;
542 /// Node2Index - Maps the node number to its topological index.
543 std::vector<int> Node2Index;
544 /// Visited - a set of nodes visited during a DFS traversal.
547 /// DFS - make a DFS traversal and mark all nodes affected by the
548 /// edge insertion. These nodes will later get new topological indexes
549 /// by means of the Shift method.
550 void DFS(const SUnit *SU, int UpperBound, bool& HasLoop);
552 /// Shift - reassign topological indexes for the nodes in the DAG
553 /// to preserve the topological ordering.
554 void Shift(BitVector& Visited, int LowerBound, int UpperBound);
556 /// Allocate - assign the topological index to the node n.
557 void Allocate(int n, int index);
560 explicit ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits);
562 /// InitDAGTopologicalSorting - create the initial topological
563 /// ordering from the DAG to be scheduled.
564 void InitDAGTopologicalSorting();
566 /// IsReachable - Checks if SU is reachable from TargetSU.
567 bool IsReachable(const SUnit *SU, const SUnit *TargetSU);
569 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU
570 /// will create a cycle.
571 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU);
573 /// AddPred - Updates the topological ordering to accomodate an edge
574 /// to be added from SUnit X to SUnit Y.
575 void AddPred(SUnit *Y, SUnit *X);
577 /// RemovePred - Updates the topological ordering to accomodate an
578 /// an edge to be removed from the specified node N from the predecessors
579 /// of the current node M.
580 void RemovePred(SUnit *M, SUnit *N);
582 typedef std::vector<int>::iterator iterator;
583 typedef std::vector<int>::const_iterator const_iterator;
584 iterator begin() { return Index2Node.begin(); }
585 const_iterator begin() const { return Index2Node.begin(); }
586 iterator end() { return Index2Node.end(); }
587 const_iterator end() const { return Index2Node.end(); }
589 typedef std::vector<int>::reverse_iterator reverse_iterator;
590 typedef std::vector<int>::const_reverse_iterator const_reverse_iterator;
591 reverse_iterator rbegin() { return Index2Node.rbegin(); }
592 const_reverse_iterator rbegin() const { return Index2Node.rbegin(); }
593 reverse_iterator rend() { return Index2Node.rend(); }
594 const_reverse_iterator rend() const { return Index2Node.rend(); }