1 //==- ScheduleDAGInstrs.h - MachineInstr Scheduling --------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAGInstrs class, which implements
11 // scheduling for a MachineInstr-based dependency graph.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
16 #define LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
18 #include "llvm/ADT/SparseSet.h"
19 #include "llvm/ADT/SparseMultiSet.h"
20 #include "llvm/CodeGen/ScheduleDAG.h"
21 #include "llvm/CodeGen/TargetSchedule.h"
22 #include "llvm/Support/Compiler.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
26 class MachineFrameInfo;
27 class MachineLoopInfo;
28 class MachineDominatorTree;
30 class RegPressureTracker;
32 /// An individual mapping from virtual register number to SUnit.
37 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
39 unsigned getSparseSetIndex() const {
40 return TargetRegisterInfo::virtReg2Index(VirtReg);
44 /// Record a physical register access.
45 /// For non data-dependent uses, OpIdx == -1.
46 struct PhysRegSUOper {
51 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
53 unsigned getSparseSetIndex() const { return Reg; }
56 /// Use a SparseMultiSet to track physical registers. Storage is only
57 /// allocated once for the pass. It can be cleared in constant time and reused
58 /// without any frees.
59 typedef SparseMultiSet<PhysRegSUOper, llvm::identity<unsigned>, uint16_t> Reg2SUnitsMap;
61 /// Use SparseSet as a SparseMap by relying on the fact that it never
62 /// compares ValueT's, only unsigned keys. This allows the set to be cleared
63 /// between scheduling regions in constant time as long as ValueT does not
64 /// require a destructor.
65 typedef SparseSet<VReg2SUnit, VirtReg2IndexFunctor> VReg2SUnitMap;
67 /// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of
69 class ScheduleDAGInstrs : public ScheduleDAG {
71 const MachineLoopInfo &MLI;
72 const MachineDominatorTree &MDT;
73 const MachineFrameInfo *MFI;
75 /// Live Intervals provides reaching defs in preRA scheduling.
78 /// TargetSchedModel provides an interface to the machine model.
79 TargetSchedModel SchedModel;
81 /// isPostRA flag indicates vregs cannot be present.
84 /// UnitLatencies (misnamed) flag avoids computing def-use latencies, using
85 /// the def-side latency only.
88 /// The standard DAG builder does not normally include terminators as DAG
89 /// nodes because it does not create the necessary dependencies to prevent
90 /// reordering. A specialized scheduler can overide
91 /// TargetInstrInfo::isSchedulingBoundary then enable this flag to indicate
92 /// it has taken responsibility for scheduling the terminator correctly.
93 bool CanHandleTerminators;
95 /// State specific to the current scheduling region.
96 /// ------------------------------------------------
98 /// The block in which to insert instructions
99 MachineBasicBlock *BB;
101 /// The beginning of the range to be scheduled.
102 MachineBasicBlock::iterator RegionBegin;
104 /// The end of the range to be scheduled.
105 MachineBasicBlock::iterator RegionEnd;
107 /// The index in BB of RegionEnd.
110 /// After calling BuildSchedGraph, each machine instruction in the current
111 /// scheduling region is mapped to an SUnit.
112 DenseMap<MachineInstr*, SUnit*> MISUnitMap;
114 /// State internal to DAG building.
115 /// -------------------------------
117 /// Defs, Uses - Remember where defs and uses of each register are as we
118 /// iterate upward through the instructions. This is allocated here instead
119 /// of inside BuildSchedGraph to avoid the need for it to be initialized and
120 /// destructed for each block.
124 /// Track the last instructon in this region defining each virtual register.
125 VReg2SUnitMap VRegDefs;
127 /// PendingLoads - Remember where unknown loads are after the most recent
128 /// unknown store, as we iterate. As with Defs and Uses, this is here
129 /// to minimize construction/destruction.
130 std::vector<SUnit *> PendingLoads;
132 /// DbgValues - Remember instruction that precedes DBG_VALUE.
133 /// These are generated by buildSchedGraph but persist so they can be
134 /// referenced when emitting the final schedule.
135 typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
137 DbgValueVector DbgValues;
138 MachineInstr *FirstDbgValue;
141 explicit ScheduleDAGInstrs(MachineFunction &mf,
142 const MachineLoopInfo &mli,
143 const MachineDominatorTree &mdt,
145 LiveIntervals *LIS = 0);
147 virtual ~ScheduleDAGInstrs() {}
149 /// \brief Get the machine model for instruction scheduling.
150 const TargetSchedModel *getSchedModel() const { return &SchedModel; }
152 /// \brief Resolve and cache a resolved scheduling class for an SUnit.
153 const MCSchedClassDesc *getSchedClass(SUnit *SU) const {
155 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
156 return SU->SchedClass;
159 /// begin - Return an iterator to the top of the current scheduling region.
160 MachineBasicBlock::iterator begin() const { return RegionBegin; }
162 /// end - Return an iterator to the bottom of the current scheduling region.
163 MachineBasicBlock::iterator end() const { return RegionEnd; }
165 /// newSUnit - Creates a new SUnit and return a ptr to it.
166 SUnit *newSUnit(MachineInstr *MI);
168 /// getSUnit - Return an existing SUnit for this MI, or NULL.
169 SUnit *getSUnit(MachineInstr *MI) const;
171 /// startBlock - Prepare to perform scheduling in the given block.
172 virtual void startBlock(MachineBasicBlock *BB);
174 /// finishBlock - Clean up after scheduling in the given block.
175 virtual void finishBlock();
177 /// Initialize the scheduler state for the next scheduling region.
178 virtual void enterRegion(MachineBasicBlock *bb,
179 MachineBasicBlock::iterator begin,
180 MachineBasicBlock::iterator end,
183 /// Notify that the scheduler has finished scheduling the current region.
184 virtual void exitRegion();
186 /// buildSchedGraph - Build SUnits from the MachineBasicBlock that we are
188 void buildSchedGraph(AliasAnalysis *AA, RegPressureTracker *RPTracker = 0);
190 /// addSchedBarrierDeps - Add dependencies from instructions in the current
191 /// list of instructions being scheduled to scheduling barrier. We want to
192 /// make sure instructions which define registers that are either used by
193 /// the terminator or are live-out are properly scheduled. This is
194 /// especially important when the definition latency of the return value(s)
195 /// are too high to be hidden by the branch or when the liveout registers
196 /// used by instructions in the fallthrough block.
197 void addSchedBarrierDeps();
199 /// schedule - Order nodes according to selected style, filling
200 /// in the Sequence member.
202 /// Typically, a scheduling algorithm will implement schedule() without
203 /// overriding enterRegion() or exitRegion().
204 virtual void schedule() = 0;
206 /// finalizeSchedule - Allow targets to perform final scheduling actions at
207 /// the level of the whole MachineFunction. By default does nothing.
208 virtual void finalizeSchedule() {}
210 virtual void dumpNode(const SUnit *SU) const;
212 /// Return a label for a DAG node that points to an instruction.
213 virtual std::string getGraphNodeLabel(const SUnit *SU) const;
215 /// Return a label for the region of code covered by the DAG.
216 virtual std::string getDAGName() const;
220 void addPhysRegDataDeps(SUnit *SU, unsigned OperIdx);
221 void addPhysRegDeps(SUnit *SU, unsigned OperIdx);
222 void addVRegDefDeps(SUnit *SU, unsigned OperIdx);
223 void addVRegUseDeps(SUnit *SU, unsigned OperIdx);
226 /// newSUnit - Creates a new SUnit and return a ptr to it.
227 inline SUnit *ScheduleDAGInstrs::newSUnit(MachineInstr *MI) {
229 const SUnit *Addr = SUnits.empty() ? 0 : &SUnits[0];
231 SUnits.push_back(SUnit(MI, (unsigned)SUnits.size()));
232 assert((Addr == 0 || Addr == &SUnits[0]) &&
233 "SUnits std::vector reallocated on the fly!");
234 SUnits.back().OrigNode = &SUnits.back();
235 return &SUnits.back();
238 /// getSUnit - Return an existing SUnit for this MI, or NULL.
239 inline SUnit *ScheduleDAGInstrs::getSUnit(MachineInstr *MI) const {
240 DenseMap<MachineInstr*, SUnit*>::const_iterator I = MISUnitMap.find(MI);
241 if (I == MISUnitMap.end())