1 //==- ScheduleDAGInstrs.h - MachineInstr Scheduling --------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAGInstrs class, which implements
11 // scheduling for a MachineInstr-based dependency graph.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
16 #define LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
18 #include "llvm/ADT/SparseMultiSet.h"
19 #include "llvm/ADT/SparseSet.h"
20 #include "llvm/CodeGen/ScheduleDAG.h"
21 #include "llvm/CodeGen/TargetSchedule.h"
22 #include "llvm/Support/Compiler.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
26 class MachineFrameInfo;
27 class MachineLoopInfo;
28 class MachineDominatorTree;
30 class RegPressureTracker;
33 /// An individual mapping from virtual register number to SUnit.
38 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
40 unsigned getSparseSetIndex() const {
41 return TargetRegisterInfo::virtReg2Index(VirtReg);
45 /// Record a physical register access.
46 /// For non-data-dependent uses, OpIdx == -1.
47 struct PhysRegSUOper {
52 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
54 unsigned getSparseSetIndex() const { return Reg; }
57 /// Use a SparseMultiSet to track physical registers. Storage is only
58 /// allocated once for the pass. It can be cleared in constant time and reused
59 /// without any frees.
60 typedef SparseMultiSet<PhysRegSUOper, llvm::identity<unsigned>, uint16_t>
63 /// Use SparseSet as a SparseMap by relying on the fact that it never
64 /// compares ValueT's, only unsigned keys. This allows the set to be cleared
65 /// between scheduling regions in constant time as long as ValueT does not
66 /// require a destructor.
67 typedef SparseSet<VReg2SUnit, VirtReg2IndexFunctor> VReg2SUnitMap;
69 /// Track local uses of virtual registers. These uses are gathered by the DAG
70 /// builder and may be consulted by the scheduler to avoid iterating an entire
72 typedef SparseMultiSet<VReg2SUnit, VirtReg2IndexFunctor> VReg2UseMap;
74 /// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of
76 class ScheduleDAGInstrs : public ScheduleDAG {
78 const MachineLoopInfo &MLI;
79 const MachineDominatorTree &MDT;
80 const MachineFrameInfo *MFI;
82 /// Live Intervals provides reaching defs in preRA scheduling.
85 /// TargetSchedModel provides an interface to the machine model.
86 TargetSchedModel SchedModel;
88 /// isPostRA flag indicates vregs cannot be present.
91 /// True if the DAG builder should remove kill flags (in preparation for
95 /// The standard DAG builder does not normally include terminators as DAG
96 /// nodes because it does not create the necessary dependencies to prevent
97 /// reordering. A specialized scheduler can overide
98 /// TargetInstrInfo::isSchedulingBoundary then enable this flag to indicate
99 /// it has taken responsibility for scheduling the terminator correctly.
100 bool CanHandleTerminators;
102 /// State specific to the current scheduling region.
103 /// ------------------------------------------------
105 /// The block in which to insert instructions
106 MachineBasicBlock *BB;
108 /// The beginning of the range to be scheduled.
109 MachineBasicBlock::iterator RegionBegin;
111 /// The end of the range to be scheduled.
112 MachineBasicBlock::iterator RegionEnd;
114 /// Instructions in this region (distance(RegionBegin, RegionEnd)).
115 unsigned NumRegionInstrs;
117 /// After calling BuildSchedGraph, each machine instruction in the current
118 /// scheduling region is mapped to an SUnit.
119 DenseMap<MachineInstr*, SUnit*> MISUnitMap;
121 /// After calling BuildSchedGraph, each vreg used in the scheduling region
122 /// is mapped to a set of SUnits. These include all local vreg uses, not
123 /// just the uses for a singly defined vreg.
124 VReg2UseMap VRegUses;
126 /// State internal to DAG building.
127 /// -------------------------------
129 /// Defs, Uses - Remember where defs and uses of each register are as we
130 /// iterate upward through the instructions. This is allocated here instead
131 /// of inside BuildSchedGraph to avoid the need for it to be initialized and
132 /// destructed for each block.
136 /// Track the last instruction in this region defining each virtual register.
137 VReg2SUnitMap VRegDefs;
139 /// PendingLoads - Remember where unknown loads are after the most recent
140 /// unknown store, as we iterate. As with Defs and Uses, this is here
141 /// to minimize construction/destruction.
142 std::vector<SUnit *> PendingLoads;
144 /// DbgValues - Remember instruction that precedes DBG_VALUE.
145 /// These are generated by buildSchedGraph but persist so they can be
146 /// referenced when emitting the final schedule.
147 typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
149 DbgValueVector DbgValues;
150 MachineInstr *FirstDbgValue;
152 /// Set of live physical registers for updating kill flags.
156 explicit ScheduleDAGInstrs(MachineFunction &mf,
157 const MachineLoopInfo &mli,
158 const MachineDominatorTree &mdt,
160 bool RemoveKillFlags = false,
161 LiveIntervals *LIS = 0);
163 virtual ~ScheduleDAGInstrs() {}
165 bool isPostRA() const { return IsPostRA; }
167 /// \brief Expose LiveIntervals for use in DAG mutators and such.
168 LiveIntervals *getLIS() const { return LIS; }
170 /// \brief Get the machine model for instruction scheduling.
171 const TargetSchedModel *getSchedModel() const { return &SchedModel; }
173 /// \brief Resolve and cache a resolved scheduling class for an SUnit.
174 const MCSchedClassDesc *getSchedClass(SUnit *SU) const {
175 if (!SU->SchedClass && SchedModel.hasInstrSchedModel())
176 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
177 return SU->SchedClass;
180 /// begin - Return an iterator to the top of the current scheduling region.
181 MachineBasicBlock::iterator begin() const { return RegionBegin; }
183 /// end - Return an iterator to the bottom of the current scheduling region.
184 MachineBasicBlock::iterator end() const { return RegionEnd; }
186 /// newSUnit - Creates a new SUnit and return a ptr to it.
187 SUnit *newSUnit(MachineInstr *MI);
189 /// getSUnit - Return an existing SUnit for this MI, or NULL.
190 SUnit *getSUnit(MachineInstr *MI) const;
192 /// startBlock - Prepare to perform scheduling in the given block.
193 virtual void startBlock(MachineBasicBlock *BB);
195 /// finishBlock - Clean up after scheduling in the given block.
196 virtual void finishBlock();
198 /// Initialize the scheduler state for the next scheduling region.
199 virtual void enterRegion(MachineBasicBlock *bb,
200 MachineBasicBlock::iterator begin,
201 MachineBasicBlock::iterator end,
202 unsigned regioninstrs);
204 /// Notify that the scheduler has finished scheduling the current region.
205 virtual void exitRegion();
207 /// buildSchedGraph - Build SUnits from the MachineBasicBlock that we are
209 void buildSchedGraph(AliasAnalysis *AA, RegPressureTracker *RPTracker = 0,
210 PressureDiffs *PDiffs = 0);
212 /// addSchedBarrierDeps - Add dependencies from instructions in the current
213 /// list of instructions being scheduled to scheduling barrier. We want to
214 /// make sure instructions which define registers that are either used by
215 /// the terminator or are live-out are properly scheduled. This is
216 /// especially important when the definition latency of the return value(s)
217 /// are too high to be hidden by the branch or when the liveout registers
218 /// used by instructions in the fallthrough block.
219 void addSchedBarrierDeps();
221 /// schedule - Order nodes according to selected style, filling
222 /// in the Sequence member.
224 /// Typically, a scheduling algorithm will implement schedule() without
225 /// overriding enterRegion() or exitRegion().
226 virtual void schedule() = 0;
228 /// finalizeSchedule - Allow targets to perform final scheduling actions at
229 /// the level of the whole MachineFunction. By default does nothing.
230 virtual void finalizeSchedule() {}
232 virtual void dumpNode(const SUnit *SU) const;
234 /// Return a label for a DAG node that points to an instruction.
235 virtual std::string getGraphNodeLabel(const SUnit *SU) const;
237 /// Return a label for the region of code covered by the DAG.
238 virtual std::string getDAGName() const;
240 /// \brief Fix register kill flags that scheduling has made invalid.
241 void fixupKills(MachineBasicBlock *MBB);
244 void addPhysRegDataDeps(SUnit *SU, unsigned OperIdx);
245 void addPhysRegDeps(SUnit *SU, unsigned OperIdx);
246 void addVRegDefDeps(SUnit *SU, unsigned OperIdx);
247 void addVRegUseDeps(SUnit *SU, unsigned OperIdx);
249 /// \brief PostRA helper for rewriting kill flags.
250 void startBlockForKills(MachineBasicBlock *BB);
252 /// \brief Toggle a register operand kill flag.
254 /// Other adjustments may be made to the instruction if necessary. Return
255 /// true if the operand has been deleted, false if not.
256 bool toggleKillFlag(MachineInstr *MI, MachineOperand &MO);
259 /// newSUnit - Creates a new SUnit and return a ptr to it.
260 inline SUnit *ScheduleDAGInstrs::newSUnit(MachineInstr *MI) {
262 const SUnit *Addr = SUnits.empty() ? 0 : &SUnits[0];
264 SUnits.push_back(SUnit(MI, (unsigned)SUnits.size()));
265 assert((Addr == 0 || Addr == &SUnits[0]) &&
266 "SUnits std::vector reallocated on the fly!");
267 SUnits.back().OrigNode = &SUnits.back();
268 return &SUnits.back();
271 /// getSUnit - Return an existing SUnit for this MI, or NULL.
272 inline SUnit *ScheduleDAGInstrs::getSUnit(MachineInstr *MI) const {
273 DenseMap<MachineInstr*, SUnit*>::const_iterator I = MISUnitMap.find(MI);
274 if (I == MISUnitMap.end())