1 //==- ScheduleDAGInstrs.h - MachineInstr Scheduling --------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAGInstrs class, which implements
11 // scheduling for a MachineInstr-based dependency graph.
13 //===----------------------------------------------------------------------===//
15 #ifndef SCHEDULEDAGINSTRS_H
16 #define SCHEDULEDAGINSTRS_H
18 #include "llvm/CodeGen/MachineDominators.h"
19 #include "llvm/CodeGen/MachineLoopInfo.h"
20 #include "llvm/CodeGen/ScheduleDAG.h"
21 #include "llvm/Support/Compiler.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/SparseSet.h"
28 class MachineLoopInfo;
29 class MachineDominatorTree;
32 /// LoopDependencies - This class analyzes loop-oriented register
33 /// dependencies, which are used to guide scheduling decisions.
34 /// For example, loop induction variable increments should be
35 /// scheduled as soon as possible after the variable's last use.
37 class LoopDependencies {
38 const MachineLoopInfo &MLI;
39 const MachineDominatorTree &MDT;
42 typedef std::map<unsigned, std::pair<const MachineOperand *, unsigned> >
46 LoopDependencies(const MachineLoopInfo &mli,
47 const MachineDominatorTree &mdt) :
50 /// VisitLoop - Clear out any previous state and analyze the given loop.
52 void VisitLoop(const MachineLoop *Loop) {
53 assert(Deps.empty() && "stale loop dependencies");
55 MachineBasicBlock *Header = Loop->getHeader();
56 SmallSet<unsigned, 8> LoopLiveIns;
57 for (MachineBasicBlock::livein_iterator LI = Header->livein_begin(),
58 LE = Header->livein_end(); LI != LE; ++LI)
59 LoopLiveIns.insert(*LI);
61 const MachineDomTreeNode *Node = MDT.getNode(Header);
62 const MachineBasicBlock *MBB = Node->getBlock();
63 assert(Loop->contains(MBB) &&
64 "Loop does not contain header!");
65 VisitRegion(Node, MBB, Loop, LoopLiveIns);
69 void VisitRegion(const MachineDomTreeNode *Node,
70 const MachineBasicBlock *MBB,
71 const MachineLoop *Loop,
72 const SmallSet<unsigned, 8> &LoopLiveIns) {
74 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
76 const MachineInstr *MI = I;
77 if (MI->isDebugValue())
79 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
80 const MachineOperand &MO = MI->getOperand(i);
81 if (!MO.isReg() || !MO.isUse())
83 unsigned MOReg = MO.getReg();
84 if (LoopLiveIns.count(MOReg))
85 Deps.insert(std::make_pair(MOReg, std::make_pair(&MO, Count)));
87 ++Count; // Not every iteration due to dbg_value above.
90 const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
91 for (std::vector<MachineDomTreeNode*>::const_iterator I =
92 Children.begin(), E = Children.end(); I != E; ++I) {
93 const MachineDomTreeNode *ChildNode = *I;
94 MachineBasicBlock *ChildBlock = ChildNode->getBlock();
95 if (Loop->contains(ChildBlock))
96 VisitRegion(ChildNode, ChildBlock, Loop, LoopLiveIns);
101 /// An individual mapping from virtual register number to SUnit.
106 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
108 unsigned getSparseSetKey() const {
109 return TargetRegisterInfo::virtReg2Index(VirtReg);
113 /// Combine a SparseSet with a 1x1 vector to track physical registers.
114 /// The SparseSet allows iterating over the (few) live registers for quickly
115 /// comparing against a regmask or clearing the set.
117 /// Storage for the map is allocated once for the pass. The map can be
118 /// cleared between scheduling regions without freeing unused entries.
119 class Reg2SUnitsMap {
120 SparseSet<unsigned> PhysRegSet;
121 std::vector<std::vector<SUnit*> > SUnits;
123 typedef SparseSet<unsigned>::const_iterator const_iterator;
125 // Allow iteration over register numbers (keys) in the map. If needed, we
126 // can provide an iterator over SUnits (values) as well.
127 const_iterator reg_begin() const { return PhysRegSet.begin(); }
128 const_iterator reg_end() const { return PhysRegSet.end(); }
130 /// Initialize the map with the number of registers.
131 /// If the map is already large enough, no allocation occurs.
132 /// For simplicity we expect the map to be empty().
133 void setRegLimit(unsigned Limit);
135 /// Returns true if the map is empty.
136 bool empty() const { return PhysRegSet.empty(); }
138 /// Clear the map without deallocating storage.
141 bool contains(unsigned Reg) const { return PhysRegSet.count(Reg); }
143 /// If this register is mapped, return its existing SUnits vector.
144 /// Otherwise map the register and return an empty SUnits vector.
145 std::vector<SUnit *> &operator[](unsigned Reg) {
146 bool New = PhysRegSet.insert(Reg).second;
147 assert((!New || SUnits[Reg].empty()) && "stale SUnits vector");
152 /// Erase an existing element without freeing memory.
153 void erase(unsigned Reg) {
154 PhysRegSet.erase(Reg);
159 /// Use SparseSet as a SparseMap by relying on the fact that it never
160 /// compares ValueT's, only unsigned keys. This allows the set to be cleared
161 /// between scheduling regions in constant time as long as ValueT does not
162 /// require a destructor.
163 typedef SparseSet<VReg2SUnit> VReg2SUnitMap;
165 /// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of
167 class ScheduleDAGInstrs : public ScheduleDAG {
169 const MachineLoopInfo &MLI;
170 const MachineDominatorTree &MDT;
171 const MachineFrameInfo *MFI;
172 const InstrItineraryData *InstrItins;
174 /// Live Intervals provides reaching defs in preRA scheduling.
177 /// isPostRA flag indicates vregs cannot be present.
180 /// UnitLatencies (misnamed) flag avoids computing def-use latencies, using
181 /// the def-side latency only.
184 /// The standard DAG builder does not normally include terminators as DAG
185 /// nodes because it does not create the necessary dependencies to prevent
186 /// reordering. A specialized scheduler can overide
187 /// TargetInstrInfo::isSchedulingBoundary then enable this flag to indicate
188 /// it has taken responsibility for scheduling the terminator correctly.
189 bool CanHandleTerminators;
191 /// State specific to the current scheduling region.
192 /// ------------------------------------------------
194 /// The block in which to insert instructions
195 MachineBasicBlock *BB;
197 /// The beginning of the range to be scheduled.
198 MachineBasicBlock::iterator RegionBegin;
200 /// The end of the range to be scheduled.
201 MachineBasicBlock::iterator RegionEnd;
203 /// The index in BB of RegionEnd.
206 /// After calling BuildSchedGraph, each machine instruction in the current
207 /// scheduling region is mapped to an SUnit.
208 DenseMap<MachineInstr*, SUnit*> MISUnitMap;
210 /// State internal to DAG building.
211 /// -------------------------------
213 /// Defs, Uses - Remember where defs and uses of each register are as we
214 /// iterate upward through the instructions. This is allocated here instead
215 /// of inside BuildSchedGraph to avoid the need for it to be initialized and
216 /// destructed for each block.
220 /// Track the last instructon in this region defining each virtual register.
221 VReg2SUnitMap VRegDefs;
223 /// PendingLoads - Remember where unknown loads are after the most recent
224 /// unknown store, as we iterate. As with Defs and Uses, this is here
225 /// to minimize construction/destruction.
226 std::vector<SUnit *> PendingLoads;
228 /// LoopRegs - Track which registers are used for loop-carried dependencies.
230 LoopDependencies LoopRegs;
232 /// DbgValues - Remember instruction that preceeds DBG_VALUE.
233 /// These are generated by buildSchedGraph but persist so they can be
234 /// referenced when emitting the final schedule.
235 typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
237 DbgValueVector DbgValues;
238 MachineInstr *FirstDbgValue;
241 explicit ScheduleDAGInstrs(MachineFunction &mf,
242 const MachineLoopInfo &mli,
243 const MachineDominatorTree &mdt,
245 LiveIntervals *LIS = 0);
247 virtual ~ScheduleDAGInstrs() {}
249 /// begin - Return an iterator to the top of the current scheduling region.
250 MachineBasicBlock::iterator begin() const { return RegionBegin; }
252 /// end - Return an iterator to the bottom of the current scheduling region.
253 MachineBasicBlock::iterator end() const { return RegionEnd; }
255 /// newSUnit - Creates a new SUnit and return a ptr to it.
256 SUnit *newSUnit(MachineInstr *MI);
258 /// getSUnit - Return an existing SUnit for this MI, or NULL.
259 SUnit *getSUnit(MachineInstr *MI) const;
261 /// startBlock - Prepare to perform scheduling in the given block.
262 virtual void startBlock(MachineBasicBlock *BB);
264 /// finishBlock - Clean up after scheduling in the given block.
265 virtual void finishBlock();
267 /// Initialize the scheduler state for the next scheduling region.
268 virtual void enterRegion(MachineBasicBlock *bb,
269 MachineBasicBlock::iterator begin,
270 MachineBasicBlock::iterator end,
273 /// Notify that the scheduler has finished scheduling the current region.
274 virtual void exitRegion();
276 /// buildSchedGraph - Build SUnits from the MachineBasicBlock that we are
278 void buildSchedGraph(AliasAnalysis *AA);
280 /// addSchedBarrierDeps - Add dependencies from instructions in the current
281 /// list of instructions being scheduled to scheduling barrier. We want to
282 /// make sure instructions which define registers that are either used by
283 /// the terminator or are live-out are properly scheduled. This is
284 /// especially important when the definition latency of the return value(s)
285 /// are too high to be hidden by the branch or when the liveout registers
286 /// used by instructions in the fallthrough block.
287 void addSchedBarrierDeps();
289 /// computeLatency - Compute node latency.
291 virtual void computeLatency(SUnit *SU);
293 /// computeOperandLatency - Override dependence edge latency using
294 /// operand use/def information
296 virtual void computeOperandLatency(SUnit *Def, SUnit *Use,
299 /// schedule - Order nodes according to selected style, filling
300 /// in the Sequence member.
302 /// Typically, a scheduling algorithm will implement schedule() without
303 /// overriding enterRegion() or exitRegion().
304 virtual void schedule() = 0;
306 /// finalizeSchedule - Allow targets to perform final scheduling actions at
307 /// the level of the whole MachineFunction. By default does nothing.
308 virtual void finalizeSchedule() {}
310 virtual void dumpNode(const SUnit *SU) const;
312 /// Return a label for a DAG node that points to an instruction.
313 virtual std::string getGraphNodeLabel(const SUnit *SU) const;
315 /// Return a label for the region of code covered by the DAG.
316 virtual std::string getDAGName() const;
320 void addPhysRegDataDeps(SUnit *SU, const MachineOperand &MO);
321 void addPhysRegDeps(SUnit *SU, unsigned OperIdx);
322 void addVRegDefDeps(SUnit *SU, unsigned OperIdx);
323 void addVRegUseDeps(SUnit *SU, unsigned OperIdx);
325 VReg2SUnitMap::iterator findVRegDef(unsigned VirtReg) {
326 return VRegDefs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
330 /// newSUnit - Creates a new SUnit and return a ptr to it.
331 inline SUnit *ScheduleDAGInstrs::newSUnit(MachineInstr *MI) {
333 const SUnit *Addr = SUnits.empty() ? 0 : &SUnits[0];
335 SUnits.push_back(SUnit(MI, (unsigned)SUnits.size()));
336 assert((Addr == 0 || Addr == &SUnits[0]) &&
337 "SUnits std::vector reallocated on the fly!");
338 SUnits.back().OrigNode = &SUnits.back();
339 return &SUnits.back();
342 /// getSUnit - Return an existing SUnit for this MI, or NULL.
343 inline SUnit *ScheduleDAGInstrs::getSUnit(MachineInstr *MI) const {
344 DenseMap<MachineInstr*, SUnit*>::const_iterator I = MISUnitMap.find(MI);
345 if (I == MISUnitMap.end())