1 //==- ScheduleDAGInstrs.h - MachineInstr Scheduling --------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAGInstrs class, which implements
11 // scheduling for a MachineInstr-based dependency graph.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
16 #define LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
18 #include "llvm/ADT/SparseSet.h"
19 #include "llvm/ADT/SparseMultiSet.h"
20 #include "llvm/CodeGen/ScheduleDAG.h"
21 #include "llvm/CodeGen/TargetSchedule.h"
22 #include "llvm/Support/Compiler.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
26 class MachineFrameInfo;
27 class MachineLoopInfo;
28 class MachineDominatorTree;
30 class RegPressureTracker;
32 /// An individual mapping from virtual register number to SUnit.
37 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
39 unsigned getSparseSetIndex() const {
40 return TargetRegisterInfo::virtReg2Index(VirtReg);
44 /// Record a physical register access.
45 /// For non data-dependent uses, OpIdx == -1.
46 struct PhysRegSUOper {
51 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
53 unsigned getSparseSetIndex() const { return Reg; }
56 /// Use a SparseMultiSet to track physical registers. Storage is only
57 /// allocated once for the pass. It can be cleared in constant time and reused
58 /// without any frees.
59 typedef SparseMultiSet<PhysRegSUOper, llvm::identity<unsigned>, uint16_t> Reg2SUnitsMap;
61 /// Use SparseSet as a SparseMap by relying on the fact that it never
62 /// compares ValueT's, only unsigned keys. This allows the set to be cleared
63 /// between scheduling regions in constant time as long as ValueT does not
64 /// require a destructor.
65 typedef SparseSet<VReg2SUnit, VirtReg2IndexFunctor> VReg2SUnitMap;
67 /// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of
69 class ScheduleDAGInstrs : public ScheduleDAG {
71 const MachineLoopInfo &MLI;
72 const MachineDominatorTree &MDT;
73 const MachineFrameInfo *MFI;
75 /// Live Intervals provides reaching defs in preRA scheduling.
78 /// TargetSchedModel provides an interface to the machine model.
79 TargetSchedModel SchedModel;
81 /// isPostRA flag indicates vregs cannot be present.
84 /// UnitLatencies (misnamed) flag avoids computing def-use latencies, using
85 /// the def-side latency only.
88 /// The standard DAG builder does not normally include terminators as DAG
89 /// nodes because it does not create the necessary dependencies to prevent
90 /// reordering. A specialized scheduler can overide
91 /// TargetInstrInfo::isSchedulingBoundary then enable this flag to indicate
92 /// it has taken responsibility for scheduling the terminator correctly.
93 bool CanHandleTerminators;
95 /// State specific to the current scheduling region.
96 /// ------------------------------------------------
98 /// The block in which to insert instructions
99 MachineBasicBlock *BB;
101 /// The beginning of the range to be scheduled.
102 MachineBasicBlock::iterator RegionBegin;
104 /// The end of the range to be scheduled.
105 MachineBasicBlock::iterator RegionEnd;
107 /// The index in BB of RegionEnd.
109 /// This is the instruction number from the top of the current block, not
110 /// the SlotIndex. It is only used by the AntiDepBreaker and should be
111 /// removed once that client is obsolete.
114 /// After calling BuildSchedGraph, each machine instruction in the current
115 /// scheduling region is mapped to an SUnit.
116 DenseMap<MachineInstr*, SUnit*> MISUnitMap;
118 /// State internal to DAG building.
119 /// -------------------------------
121 /// Defs, Uses - Remember where defs and uses of each register are as we
122 /// iterate upward through the instructions. This is allocated here instead
123 /// of inside BuildSchedGraph to avoid the need for it to be initialized and
124 /// destructed for each block.
128 /// Track the last instructon in this region defining each virtual register.
129 VReg2SUnitMap VRegDefs;
131 /// PendingLoads - Remember where unknown loads are after the most recent
132 /// unknown store, as we iterate. As with Defs and Uses, this is here
133 /// to minimize construction/destruction.
134 std::vector<SUnit *> PendingLoads;
136 /// DbgValues - Remember instruction that precedes DBG_VALUE.
137 /// These are generated by buildSchedGraph but persist so they can be
138 /// referenced when emitting the final schedule.
139 typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
141 DbgValueVector DbgValues;
142 MachineInstr *FirstDbgValue;
145 explicit ScheduleDAGInstrs(MachineFunction &mf,
146 const MachineLoopInfo &mli,
147 const MachineDominatorTree &mdt,
149 LiveIntervals *LIS = 0);
151 virtual ~ScheduleDAGInstrs() {}
153 /// \brief Expose LiveIntervals for use in DAG mutators and such.
154 LiveIntervals *getLIS() const { return LIS; }
156 /// \brief Get the machine model for instruction scheduling.
157 const TargetSchedModel *getSchedModel() const { return &SchedModel; }
159 /// \brief Resolve and cache a resolved scheduling class for an SUnit.
160 const MCSchedClassDesc *getSchedClass(SUnit *SU) const {
161 if (!SU->SchedClass && SchedModel.hasInstrSchedModel())
162 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
163 return SU->SchedClass;
166 /// begin - Return an iterator to the top of the current scheduling region.
167 MachineBasicBlock::iterator begin() const { return RegionBegin; }
169 /// end - Return an iterator to the bottom of the current scheduling region.
170 MachineBasicBlock::iterator end() const { return RegionEnd; }
172 /// newSUnit - Creates a new SUnit and return a ptr to it.
173 SUnit *newSUnit(MachineInstr *MI);
175 /// getSUnit - Return an existing SUnit for this MI, or NULL.
176 SUnit *getSUnit(MachineInstr *MI) const;
178 /// startBlock - Prepare to perform scheduling in the given block.
179 virtual void startBlock(MachineBasicBlock *BB);
181 /// finishBlock - Clean up after scheduling in the given block.
182 virtual void finishBlock();
184 /// Initialize the scheduler state for the next scheduling region.
185 virtual void enterRegion(MachineBasicBlock *bb,
186 MachineBasicBlock::iterator begin,
187 MachineBasicBlock::iterator end,
190 /// Notify that the scheduler has finished scheduling the current region.
191 virtual void exitRegion();
193 /// buildSchedGraph - Build SUnits from the MachineBasicBlock that we are
195 void buildSchedGraph(AliasAnalysis *AA, RegPressureTracker *RPTracker = 0);
197 /// addSchedBarrierDeps - Add dependencies from instructions in the current
198 /// list of instructions being scheduled to scheduling barrier. We want to
199 /// make sure instructions which define registers that are either used by
200 /// the terminator or are live-out are properly scheduled. This is
201 /// especially important when the definition latency of the return value(s)
202 /// are too high to be hidden by the branch or when the liveout registers
203 /// used by instructions in the fallthrough block.
204 void addSchedBarrierDeps();
206 /// schedule - Order nodes according to selected style, filling
207 /// in the Sequence member.
209 /// Typically, a scheduling algorithm will implement schedule() without
210 /// overriding enterRegion() or exitRegion().
211 virtual void schedule() = 0;
213 /// finalizeSchedule - Allow targets to perform final scheduling actions at
214 /// the level of the whole MachineFunction. By default does nothing.
215 virtual void finalizeSchedule() {}
217 virtual void dumpNode(const SUnit *SU) const;
219 /// Return a label for a DAG node that points to an instruction.
220 virtual std::string getGraphNodeLabel(const SUnit *SU) const;
222 /// Return a label for the region of code covered by the DAG.
223 virtual std::string getDAGName() const;
227 void addPhysRegDataDeps(SUnit *SU, unsigned OperIdx);
228 void addPhysRegDeps(SUnit *SU, unsigned OperIdx);
229 void addVRegDefDeps(SUnit *SU, unsigned OperIdx);
230 void addVRegUseDeps(SUnit *SU, unsigned OperIdx);
233 /// newSUnit - Creates a new SUnit and return a ptr to it.
234 inline SUnit *ScheduleDAGInstrs::newSUnit(MachineInstr *MI) {
236 const SUnit *Addr = SUnits.empty() ? 0 : &SUnits[0];
238 SUnits.push_back(SUnit(MI, (unsigned)SUnits.size()));
239 assert((Addr == 0 || Addr == &SUnits[0]) &&
240 "SUnits std::vector reallocated on the fly!");
241 SUnits.back().OrigNode = &SUnits.back();
242 return &SUnits.back();
245 /// getSUnit - Return an existing SUnit for this MI, or NULL.
246 inline SUnit *ScheduleDAGInstrs::getSUnit(MachineInstr *MI) const {
247 DenseMap<MachineInstr*, SUnit*>::const_iterator I = MISUnitMap.find(MI);
248 if (I == MISUnitMap.end())