1 //==- ScheduleDAGInstrs.h - MachineInstr Scheduling --------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAGInstrs class, which implements
11 // scheduling for a MachineInstr-based dependency graph.
13 //===----------------------------------------------------------------------===//
15 #ifndef SCHEDULEDAGINSTRS_H
16 #define SCHEDULEDAGINSTRS_H
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/SparseSet.h"
20 #include "llvm/CodeGen/MachineDominators.h"
21 #include "llvm/CodeGen/MachineLoopInfo.h"
22 #include "llvm/CodeGen/ScheduleDAG.h"
23 #include "llvm/CodeGen/TargetSchedule.h"
24 #include "llvm/Support/Compiler.h"
25 #include "llvm/Target/TargetRegisterInfo.h"
29 class MachineLoopInfo;
30 class MachineDominatorTree;
32 class RegPressureTracker;
34 /// An individual mapping from virtual register number to SUnit.
39 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
41 unsigned getSparseSetIndex() const {
42 return TargetRegisterInfo::virtReg2Index(VirtReg);
46 /// Record a physical register access.
47 /// For non data-dependent uses, OpIdx == -1.
48 struct PhysRegSUOper {
52 PhysRegSUOper(SUnit *su, int op): SU(su), OpIdx(op) {}
55 /// Combine a SparseSet with a 1x1 vector to track physical registers.
56 /// The SparseSet allows iterating over the (few) live registers for quickly
57 /// comparing against a regmask or clearing the set.
59 /// Storage for the map is allocated once for the pass. The map can be
60 /// cleared between scheduling regions without freeing unused entries.
62 SparseSet<unsigned> PhysRegSet;
63 std::vector<std::vector<PhysRegSUOper> > SUnits;
65 typedef SparseSet<unsigned>::const_iterator const_iterator;
67 // Allow iteration over register numbers (keys) in the map. If needed, we
68 // can provide an iterator over SUnits (values) as well.
69 const_iterator reg_begin() const { return PhysRegSet.begin(); }
70 const_iterator reg_end() const { return PhysRegSet.end(); }
72 /// Initialize the map with the number of registers.
73 /// If the map is already large enough, no allocation occurs.
74 /// For simplicity we expect the map to be empty().
75 void setRegLimit(unsigned Limit);
77 /// Returns true if the map is empty.
78 bool empty() const { return PhysRegSet.empty(); }
80 /// Clear the map without deallocating storage.
83 bool contains(unsigned Reg) const { return PhysRegSet.count(Reg); }
85 /// If this register is mapped, return its existing SUnits vector.
86 /// Otherwise map the register and return an empty SUnits vector.
87 std::vector<PhysRegSUOper> &operator[](unsigned Reg) {
88 bool New = PhysRegSet.insert(Reg).second;
89 assert((!New || SUnits[Reg].empty()) && "stale SUnits vector");
94 /// Erase an existing element without freeing memory.
95 void erase(unsigned Reg) {
96 PhysRegSet.erase(Reg);
101 /// Use SparseSet as a SparseMap by relying on the fact that it never
102 /// compares ValueT's, only unsigned keys. This allows the set to be cleared
103 /// between scheduling regions in constant time as long as ValueT does not
104 /// require a destructor.
105 typedef SparseSet<VReg2SUnit, VirtReg2IndexFunctor> VReg2SUnitMap;
107 /// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of
109 class ScheduleDAGInstrs : public ScheduleDAG {
111 const MachineLoopInfo &MLI;
112 const MachineDominatorTree &MDT;
113 const MachineFrameInfo *MFI;
115 /// Live Intervals provides reaching defs in preRA scheduling.
118 /// TargetSchedModel provides an interface to the machine model.
119 TargetSchedModel SchedModel;
121 /// isPostRA flag indicates vregs cannot be present.
124 /// UnitLatencies (misnamed) flag avoids computing def-use latencies, using
125 /// the def-side latency only.
128 /// The standard DAG builder does not normally include terminators as DAG
129 /// nodes because it does not create the necessary dependencies to prevent
130 /// reordering. A specialized scheduler can overide
131 /// TargetInstrInfo::isSchedulingBoundary then enable this flag to indicate
132 /// it has taken responsibility for scheduling the terminator correctly.
133 bool CanHandleTerminators;
135 /// State specific to the current scheduling region.
136 /// ------------------------------------------------
138 /// The block in which to insert instructions
139 MachineBasicBlock *BB;
141 /// The beginning of the range to be scheduled.
142 MachineBasicBlock::iterator RegionBegin;
144 /// The end of the range to be scheduled.
145 MachineBasicBlock::iterator RegionEnd;
147 /// The index in BB of RegionEnd.
150 /// After calling BuildSchedGraph, each machine instruction in the current
151 /// scheduling region is mapped to an SUnit.
152 DenseMap<MachineInstr*, SUnit*> MISUnitMap;
154 /// State internal to DAG building.
155 /// -------------------------------
157 /// Defs, Uses - Remember where defs and uses of each register are as we
158 /// iterate upward through the instructions. This is allocated here instead
159 /// of inside BuildSchedGraph to avoid the need for it to be initialized and
160 /// destructed for each block.
164 /// Track the last instructon in this region defining each virtual register.
165 VReg2SUnitMap VRegDefs;
167 /// PendingLoads - Remember where unknown loads are after the most recent
168 /// unknown store, as we iterate. As with Defs and Uses, this is here
169 /// to minimize construction/destruction.
170 std::vector<SUnit *> PendingLoads;
172 /// DbgValues - Remember instruction that precedes DBG_VALUE.
173 /// These are generated by buildSchedGraph but persist so they can be
174 /// referenced when emitting the final schedule.
175 typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
177 DbgValueVector DbgValues;
178 MachineInstr *FirstDbgValue;
181 explicit ScheduleDAGInstrs(MachineFunction &mf,
182 const MachineLoopInfo &mli,
183 const MachineDominatorTree &mdt,
185 LiveIntervals *LIS = 0);
187 virtual ~ScheduleDAGInstrs() {}
189 /// \brief Get the machine model for instruction scheduling.
190 const TargetSchedModel *getSchedModel() const { return &SchedModel; }
192 /// \brief Resolve and cache a resolved scheduling class for an SUnit.
193 const MCSchedClassDesc *getSchedClass(SUnit *SU) const {
195 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
196 return SU->SchedClass;
199 /// begin - Return an iterator to the top of the current scheduling region.
200 MachineBasicBlock::iterator begin() const { return RegionBegin; }
202 /// end - Return an iterator to the bottom of the current scheduling region.
203 MachineBasicBlock::iterator end() const { return RegionEnd; }
205 /// newSUnit - Creates a new SUnit and return a ptr to it.
206 SUnit *newSUnit(MachineInstr *MI);
208 /// getSUnit - Return an existing SUnit for this MI, or NULL.
209 SUnit *getSUnit(MachineInstr *MI) const;
211 /// startBlock - Prepare to perform scheduling in the given block.
212 virtual void startBlock(MachineBasicBlock *BB);
214 /// finishBlock - Clean up after scheduling in the given block.
215 virtual void finishBlock();
217 /// Initialize the scheduler state for the next scheduling region.
218 virtual void enterRegion(MachineBasicBlock *bb,
219 MachineBasicBlock::iterator begin,
220 MachineBasicBlock::iterator end,
223 /// Notify that the scheduler has finished scheduling the current region.
224 virtual void exitRegion();
226 /// buildSchedGraph - Build SUnits from the MachineBasicBlock that we are
228 void buildSchedGraph(AliasAnalysis *AA, RegPressureTracker *RPTracker = 0);
230 /// addSchedBarrierDeps - Add dependencies from instructions in the current
231 /// list of instructions being scheduled to scheduling barrier. We want to
232 /// make sure instructions which define registers that are either used by
233 /// the terminator or are live-out are properly scheduled. This is
234 /// especially important when the definition latency of the return value(s)
235 /// are too high to be hidden by the branch or when the liveout registers
236 /// used by instructions in the fallthrough block.
237 void addSchedBarrierDeps();
239 /// schedule - Order nodes according to selected style, filling
240 /// in the Sequence member.
242 /// Typically, a scheduling algorithm will implement schedule() without
243 /// overriding enterRegion() or exitRegion().
244 virtual void schedule() = 0;
246 /// finalizeSchedule - Allow targets to perform final scheduling actions at
247 /// the level of the whole MachineFunction. By default does nothing.
248 virtual void finalizeSchedule() {}
250 virtual void dumpNode(const SUnit *SU) const;
252 /// Return a label for a DAG node that points to an instruction.
253 virtual std::string getGraphNodeLabel(const SUnit *SU) const;
255 /// Return a label for the region of code covered by the DAG.
256 virtual std::string getDAGName() const;
260 void addPhysRegDataDeps(SUnit *SU, unsigned OperIdx);
261 void addPhysRegDeps(SUnit *SU, unsigned OperIdx);
262 void addVRegDefDeps(SUnit *SU, unsigned OperIdx);
263 void addVRegUseDeps(SUnit *SU, unsigned OperIdx);
266 /// newSUnit - Creates a new SUnit and return a ptr to it.
267 inline SUnit *ScheduleDAGInstrs::newSUnit(MachineInstr *MI) {
269 const SUnit *Addr = SUnits.empty() ? 0 : &SUnits[0];
271 SUnits.push_back(SUnit(MI, (unsigned)SUnits.size()));
272 assert((Addr == 0 || Addr == &SUnits[0]) &&
273 "SUnits std::vector reallocated on the fly!");
274 SUnits.back().OrigNode = &SUnits.back();
275 return &SUnits.back();
278 /// getSUnit - Return an existing SUnit for this MI, or NULL.
279 inline SUnit *ScheduleDAGInstrs::getSUnit(MachineInstr *MI) const {
280 DenseMap<MachineInstr*, SUnit*>::const_iterator I = MISUnitMap.find(MI);
281 if (I == MISUnitMap.end())