1 //===-- llvm/CodeGen/SchedulerRegistry.h ------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation for instruction scheduler function
11 // pass registry (RegisterScheduler).
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SCHEDULERREGISTRY_H
16 #define LLVM_CODEGEN_SCHEDULERREGISTRY_H
18 #include "llvm/CodeGen/MachinePassRegistry.h"
19 #include "llvm/Target/TargetMachine.h"
23 //===----------------------------------------------------------------------===//
25 /// RegisterScheduler class - Track the registration of instruction schedulers.
27 //===----------------------------------------------------------------------===//
29 class SelectionDAGISel;
30 class ScheduleDAGSDNodes;
32 class MachineBasicBlock;
34 class RegisterScheduler : public MachinePassRegistryNode {
36 typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*,
39 static MachinePassRegistry Registry;
41 RegisterScheduler(const char *N, const char *D, FunctionPassCtor C)
42 : MachinePassRegistryNode(N, D, (MachinePassCtor)C)
43 { Registry.Add(this); }
44 ~RegisterScheduler() { Registry.Remove(this); }
49 RegisterScheduler *getNext() const {
50 return (RegisterScheduler *)MachinePassRegistryNode::getNext();
52 static RegisterScheduler *getList() {
53 return (RegisterScheduler *)Registry.getList();
55 static FunctionPassCtor getDefault() {
56 return (FunctionPassCtor)Registry.getDefault();
58 static void setDefault(FunctionPassCtor C) {
59 Registry.setDefault((MachinePassCtor)C);
61 static void setListener(MachinePassRegistryListener *L) {
62 Registry.setListener(L);
66 /// createBURRListDAGScheduler - This creates a bottom up register usage
67 /// reduction list scheduler.
68 ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
69 CodeGenOpt::Level OptLevel);
71 /// createBURRListDAGScheduler - This creates a bottom up list scheduler that
72 /// schedules nodes in source code order when possible.
73 ScheduleDAGSDNodes *createSourceListDAGScheduler(SelectionDAGISel *IS,
74 CodeGenOpt::Level OptLevel);
76 /// createHybridListDAGScheduler - This creates a bottom up register pressure
77 /// aware list scheduler that make use of latency information to avoid stalls
78 /// for long latency instructions in low register pressure mode. In high
79 /// register pressure mode it schedules to reduce register pressure.
80 ScheduleDAGSDNodes *createHybridListDAGScheduler(SelectionDAGISel *IS,
83 /// createILPListDAGScheduler - This creates a bottom up register pressure
84 /// aware list scheduler that tries to increase instruction level parallelism
85 /// in low register pressure mode. In high register pressure mode it schedules
86 /// to reduce register pressure.
87 ScheduleDAGSDNodes *createILPListDAGScheduler(SelectionDAGISel *IS,
90 /// createFastDAGScheduler - This creates a "fast" scheduler.
92 ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
93 CodeGenOpt::Level OptLevel);
95 /// createVLIWDAGScheduler - Scheduler for VLIW targets. This creates top down
96 /// DFA driven list scheduler with clustering heuristic to control
97 /// register pressure.
98 ScheduleDAGSDNodes *createVLIWDAGScheduler(SelectionDAGISel *IS,
99 CodeGenOpt::Level OptLevel);
100 /// createDefaultScheduler - This creates an instruction scheduler appropriate
102 ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
103 CodeGenOpt::Level OptLevel);
105 /// createDAGLinearizer - This creates a "no-scheduling" scheduler which
106 /// linearize the DAG using topological order.
107 ScheduleDAGSDNodes *createDAGLinearizer(SelectionDAGISel *IS,
108 CodeGenOpt::Level OptLevel);
110 } // end namespace llvm