1 //===-- llvm/CodeGen/SchedulerRegistry.h ------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation for instruction scheduler function
11 // pass registry (RegisterScheduler).
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SCHEDULERREGISTRY_H
16 #define LLVM_CODEGEN_SCHEDULERREGISTRY_H
18 #include "llvm/CodeGen/MachinePassRegistry.h"
19 #include "llvm/Target/TargetMachine.h"
23 //===----------------------------------------------------------------------===//
25 /// RegisterScheduler class - Track the registration of instruction schedulers.
27 //===----------------------------------------------------------------------===//
29 class SelectionDAGISel;
30 class ScheduleDAGSDNodes;
32 class MachineBasicBlock;
34 class RegisterScheduler : public MachinePassRegistryNode {
36 typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*,
39 static MachinePassRegistry Registry;
41 RegisterScheduler(const char *N, const char *D, FunctionPassCtor C)
42 : MachinePassRegistryNode(N, D, (MachinePassCtor)C)
43 { Registry.Add(this); }
44 ~RegisterScheduler() { Registry.Remove(this); }
49 RegisterScheduler *getNext() const {
50 return (RegisterScheduler *)MachinePassRegistryNode::getNext();
52 static RegisterScheduler *getList() {
53 return (RegisterScheduler *)Registry.getList();
55 static void setListener(MachinePassRegistryListener *L) {
56 Registry.setListener(L);
60 /// createBURRListDAGScheduler - This creates a bottom up register usage
61 /// reduction list scheduler.
62 ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
63 CodeGenOpt::Level OptLevel);
65 /// createBURRListDAGScheduler - This creates a bottom up list scheduler that
66 /// schedules nodes in source code order when possible.
67 ScheduleDAGSDNodes *createSourceListDAGScheduler(SelectionDAGISel *IS,
68 CodeGenOpt::Level OptLevel);
70 /// createHybridListDAGScheduler - This creates a bottom up register pressure
71 /// aware list scheduler that make use of latency information to avoid stalls
72 /// for long latency instructions in low register pressure mode. In high
73 /// register pressure mode it schedules to reduce register pressure.
74 ScheduleDAGSDNodes *createHybridListDAGScheduler(SelectionDAGISel *IS,
77 /// createILPListDAGScheduler - This creates a bottom up register pressure
78 /// aware list scheduler that tries to increase instruction level parallelism
79 /// in low register pressure mode. In high register pressure mode it schedules
80 /// to reduce register pressure.
81 ScheduleDAGSDNodes *createILPListDAGScheduler(SelectionDAGISel *IS,
84 /// createFastDAGScheduler - This creates a "fast" scheduler.
86 ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
87 CodeGenOpt::Level OptLevel);
89 /// createVLIWDAGScheduler - Scheduler for VLIW targets. This creates top down
90 /// DFA driven list scheduler with clustering heuristic to control
91 /// register pressure.
92 ScheduleDAGSDNodes *createVLIWDAGScheduler(SelectionDAGISel *IS,
93 CodeGenOpt::Level OptLevel);
94 /// createDefaultScheduler - This creates an instruction scheduler appropriate
96 ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
97 CodeGenOpt::Level OptLevel);
99 /// createDAGLinearizer - This creates a "no-scheduling" scheduler which
100 /// linearize the DAG using topological order.
101 ScheduleDAGSDNodes *createDAGLinearizer(SelectionDAGISel *IS,
102 CodeGenOpt::Level OptLevel);
104 } // end namespace llvm