1 //===-- llvm/CodeGen/SchedulerRegistry.h ------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation for instruction scheduler function
11 // pass registry (RegisterScheduler).
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGENSCHEDULERREGISTRY_H
16 #define LLVM_CODEGENSCHEDULERREGISTRY_H
18 #include "llvm/CodeGen/MachinePassRegistry.h"
22 //===----------------------------------------------------------------------===//
24 /// RegisterScheduler class - Track the registration of instruction schedulers.
26 //===----------------------------------------------------------------------===//
28 class SelectionDAGISel;
31 class MachineBasicBlock;
33 class RegisterScheduler : public MachinePassRegistryNode {
35 typedef ScheduleDAG *(*FunctionPassCtor)(SelectionDAGISel*, bool);
37 static MachinePassRegistry Registry;
39 RegisterScheduler(const char *N, const char *D, FunctionPassCtor C)
40 : MachinePassRegistryNode(N, D, (MachinePassCtor)C)
41 { Registry.Add(this); }
42 ~RegisterScheduler() { Registry.Remove(this); }
47 RegisterScheduler *getNext() const {
48 return (RegisterScheduler *)MachinePassRegistryNode::getNext();
50 static RegisterScheduler *getList() {
51 return (RegisterScheduler *)Registry.getList();
53 static FunctionPassCtor getDefault() {
54 return (FunctionPassCtor)Registry.getDefault();
56 static void setDefault(FunctionPassCtor C) {
57 Registry.setDefault((MachinePassCtor)C);
59 static void setListener(MachinePassRegistryListener *L) {
60 Registry.setListener(L);
64 /// createBURRListDAGScheduler - This creates a bottom up register usage
65 /// reduction list scheduler.
66 ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS,
69 /// createTDRRListDAGScheduler - This creates a top down register usage
70 /// reduction list scheduler.
71 ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS,
74 /// createTDListDAGScheduler - This creates a top-down list scheduler with
75 /// a hazard recognizer.
76 ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS,
79 /// createFastDAGScheduler - This creates a "fast" scheduler.
81 ScheduleDAG *createFastDAGScheduler(SelectionDAGISel *IS,
84 /// createDefaultScheduler - This creates an instruction scheduler appropriate
86 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
89 } // end namespace llvm