include/llvm/CodeGen/SchedulerRegistry.h

   1 //===-- llvm/CodeGen/SchedulerRegistry.h ------------------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the implementation for instruction scheduler function
  11 // pass registry (RegisterScheduler).
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef LLVM_CODEGENSCHEDULERREGISTRY_H
  16 #define LLVM_CODEGENSCHEDULERREGISTRY_H
  17
  18 #include "llvm/CodeGen/MachinePassRegistry.h"
  19
  20 namespace llvm {
  21
  22 //===----------------------------------------------------------------------===//
  23 ///
  24 /// RegisterScheduler class - Track the registration of instruction schedulers.
  25 ///
  26 //===----------------------------------------------------------------------===//
  27
  28 class SelectionDAGISel;
  29 class ScheduleDAG;
  30 class SelectionDAG;
  31 class MachineBasicBlock;
  32
  33 class RegisterScheduler : public MachinePassRegistryNode {
  34 public:
  35   typedef ScheduleDAG *(*FunctionPassCtor)(SelectionDAGISel*, SelectionDAG*,
  36                                         const TargetMachine *,
  37                                         MachineBasicBlock*, bool);
  38
  39   static MachinePassRegistry Registry;
  40
  41   RegisterScheduler(const char *N, const char *D, FunctionPassCtor C)
  42   : MachinePassRegistryNode(N, D, (MachinePassCtor)C)
  43   { Registry.Add(this); }
  44   ~RegisterScheduler() { Registry.Remove(this); }
  45
  46
  47   // Accessors.
  48   //
  49   RegisterScheduler *getNext() const {
  50     return (RegisterScheduler *)MachinePassRegistryNode::getNext();
  51   }
  52   static RegisterScheduler *getList() {
  53     return (RegisterScheduler *)Registry.getList();
  54   }
  55   static FunctionPassCtor getDefault() {
  56     return (FunctionPassCtor)Registry.getDefault();
  57   }
  58   static void setDefault(FunctionPassCtor C) {
  59     Registry.setDefault((MachinePassCtor)C);
  60   }
  61   static void setListener(MachinePassRegistryListener *L) {
  62     Registry.setListener(L);
  63   }
  64 };
  65
  66 /// createBURRListDAGScheduler - This creates a bottom up register usage
  67 /// reduction list scheduler.
  68 ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS,
  69                                         SelectionDAG *DAG,
  70                                         const TargetMachine *TM,
  71                                         MachineBasicBlock *BB,
  72                                         bool Fast);
  73
  74 /// createTDRRListDAGScheduler - This creates a top down register usage
  75 /// reduction list scheduler.
  76 ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS,
  77                                         SelectionDAG *DAG,
  78                                         const TargetMachine *TM,
  79                                         MachineBasicBlock *BB,
  80                                         bool Fast);
  81
  82 /// createTDListDAGScheduler - This creates a top-down list scheduler with
  83 /// a hazard recognizer.
  84 ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS,
  85                                       SelectionDAG *DAG,
  86                                       const TargetMachine *TM,
  87                                       MachineBasicBlock *BB,
  88                                       bool Fast);
  89
  90 /// createFastDAGScheduler - This creates a "fast" scheduler.
  91 ///
  92 ScheduleDAG *createFastDAGScheduler(SelectionDAGISel *IS,
  93                                     SelectionDAG *DAG,
  94                                     const TargetMachine *TM,
  95                                     MachineBasicBlock *BB,
  96                                     bool Fast);
  97
  98 /// createDefaultScheduler - This creates an instruction scheduler appropriate
  99 /// for the target.
 100 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
 101                                     SelectionDAG *DAG,
 102                                     const TargetMachine *TM,
 103                                     MachineBasicBlock *BB,
 104                                     bool Fast);
 105
 106 } // end namespace llvm
 107
 108
 109 #endif