include/llvm/CodeGen/SchedulerRegistry.h

   1 //===-- llvm/CodeGen/SchedulerRegistry.h ------------------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the implementation for instruction scheduler function
  11 // pass registry (RegisterScheduler).
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef LLVM_CODEGENSCHEDULERREGISTRY_H
  16 #define LLVM_CODEGENSCHEDULERREGISTRY_H
  17
  18 #include "llvm/CodeGen/MachinePassRegistry.h"
  19
  20 namespace llvm {
  21
  22 //===----------------------------------------------------------------------===//
  23 ///
  24 /// RegisterScheduler class - Track the registration of instruction schedulers.
  25 ///
  26 //===----------------------------------------------------------------------===//
  27
  28 class SelectionDAGISel;
  29 class ScheduleDAGSDNodes;
  30 class SelectionDAG;
  31 class MachineBasicBlock;
  32
  33 class RegisterScheduler : public MachinePassRegistryNode {
  34 public:
  35   typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, unsigned);
  36
  37   static MachinePassRegistry Registry;
  38
  39   RegisterScheduler(const char *N, const char *D, FunctionPassCtor C)
  40   : MachinePassRegistryNode(N, D, (MachinePassCtor)C)
  41   { Registry.Add(this); }
  42   ~RegisterScheduler() { Registry.Remove(this); }
  43
  44
  45   // Accessors.
  46   //
  47   RegisterScheduler *getNext() const {
  48     return (RegisterScheduler *)MachinePassRegistryNode::getNext();
  49   }
  50   static RegisterScheduler *getList() {
  51     return (RegisterScheduler *)Registry.getList();
  52   }
  53   static FunctionPassCtor getDefault() {
  54     return (FunctionPassCtor)Registry.getDefault();
  55   }
  56   static void setDefault(FunctionPassCtor C) {
  57     Registry.setDefault((MachinePassCtor)C);
  58   }
  59   static void setListener(MachinePassRegistryListener *L) {
  60     Registry.setListener(L);
  61   }
  62 };
  63
  64 /// createBURRListDAGScheduler - This creates a bottom up register usage
  65 /// reduction list scheduler.
  66 ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
  67                                                unsigned OptLevel);
  68
  69 /// createTDRRListDAGScheduler - This creates a top down register usage
  70 /// reduction list scheduler.
  71 ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
  72                                                unsigned OptLevel);
  73
  74 /// createTDListDAGScheduler - This creates a top-down list scheduler with
  75 /// a hazard recognizer.
  76 ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
  77                                              unsigned OptLevel);
  78
  79 /// createFastDAGScheduler - This creates a "fast" scheduler.
  80 ///
  81 ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
  82                                            unsigned OptLevel);
  83
  84 /// createDefaultScheduler - This creates an instruction scheduler appropriate
  85 /// for the target.
  86 ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
  87                                            unsigned OptLevel);
  88
  89 } // end namespace llvm
  90
  91 #endif