1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
18 #include "llvm/Pass.h"
19 #include "llvm/Constant.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/SelectionDAGNodes.h"
24 class SelectionDAGLowering;
27 class MachineBasicBlock;
28 class MachineFunction;
31 class FunctionLoweringInfo;
32 class HazardRecognizer;
34 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
35 /// pattern-matching instruction selectors.
36 class SelectionDAGISel : public FunctionPass {
41 MachineBasicBlock *BB;
42 std::vector<SDNode*> TopOrder;
46 explicit SelectionDAGISel(TargetLowering &tli) :
47 FunctionPass((intptr_t)&ID), TLI(tli), DAGSize(0) {}
49 TargetLowering &getTargetLowering() { return TLI; }
51 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
53 virtual bool runOnFunction(Function &Fn);
55 unsigned MakeReg(MVT::ValueType VT);
57 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
58 virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;
59 virtual void SelectRootInit() {
60 DAGSize = CurDAG->AssignTopologicalOrder(TopOrder);
63 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
64 /// addressing mode, according to the specified constraint code. If this does
65 /// not match or is not implemented, return true. The resultant operands
66 /// (which will appear in the machine instruction) should be added to the
68 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
70 std::vector<SDOperand> &OutOps,
75 /// CanBeFoldedBy - Returns true if the specific operand node N of U can be
76 /// folded during instruction selection that starts at Root?
77 virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const {
81 /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
82 /// to use for this target when scheduling the DAG.
83 virtual HazardRecognizer *CreateTargetHazardRecognizer();
85 /// CaseBlock - This structure is used to communicate between SDLowering and
86 /// SDISel for the code generation of additional basic blocks needed by multi-
87 /// case switch statements.
89 CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle,
90 MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
91 MachineBasicBlock *me)
92 : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
93 TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
94 // CC - the condition code to use for the case block's setcc node
96 // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
97 // Emit by default LHS op RHS. MHS is used for range comparisons:
98 // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
99 Value *CmpLHS, *CmpMHS, *CmpRHS;
100 // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
101 MachineBasicBlock *TrueBB, *FalseBB;
102 // ThisBB - the block into which to emit the code for the setcc and branches
103 MachineBasicBlock *ThisBB;
106 JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
107 MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {};
109 /// Reg - the virtual register containing the index of the jump table entry
112 /// JTI - the JumpTableIndex for this jump table in the function.
114 /// MBB - the MBB into which to emit the code for the indirect jump.
115 MachineBasicBlock *MBB;
116 /// Default - the MBB of the default bb, which is a successor of the range
117 /// check MBB. This is when updating PHI nodes in successors.
118 MachineBasicBlock *Default;
120 struct JumpTableHeader {
121 JumpTableHeader(uint64_t F, uint64_t L, Value* SV, MachineBasicBlock* H,
123 First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {};
127 MachineBasicBlock *HeaderBB;
130 typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
133 BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
134 Mask(M), ThisBB(T), TargetBB(Tr) { };
136 MachineBasicBlock* ThisBB;
137 MachineBasicBlock* TargetBB;
140 typedef SmallVector<BitTestCase, 3> BitTestInfo;
142 struct BitTestBlock {
143 BitTestBlock(uint64_t F, uint64_t R, Value* SV,
145 MachineBasicBlock* P, MachineBasicBlock* D,
146 const BitTestInfo& C):
147 First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
148 Parent(P), Default(D), Cases(C) { };
154 MachineBasicBlock *Parent;
155 MachineBasicBlock *Default;
159 /// Pick a safe ordering and emit instructions for each target node in the
161 void ScheduleAndEmitDAG(SelectionDAG &DAG);
163 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
164 /// by tblgen. Others should not call it.
165 void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
168 // Calls to these predicates are generated by tblgen.
169 bool CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
170 int64_t DesiredMaskS) const;
171 bool CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
172 int64_t DesiredMaskS) const;
175 void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF,
176 FunctionLoweringInfo &FuncInfo);
178 void BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
179 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
180 FunctionLoweringInfo &FuncInfo);
181 void CodeGenAndEmitDAG(SelectionDAG &DAG);
182 void LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
183 std::vector<SDOperand> &UnorderedChains);
185 /// SwitchCases - Vector of CaseBlock structures used to communicate
186 /// SwitchInst code generation information.
187 std::vector<CaseBlock> SwitchCases;
189 /// JTCases - Vector of JumpTable structures which holds necessary information
190 /// for emitting a jump tables during SwitchInst code generation.
191 std::vector<JumpTableBlock> JTCases;
193 std::vector<BitTestBlock> BitTestCases;
198 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */