1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
18 #include "llvm/Pass.h"
19 #include "llvm/Constant.h"
20 #include "llvm/CodeGen/SelectionDAGNodes.h"
24 class SelectionDAGLowering;
27 class MachineBasicBlock;
28 class MachineFunction;
31 class FunctionLoweringInfo;
32 class HazardRecognizer;
34 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
35 /// pattern-matching instruction selectors.
36 class SelectionDAGISel : public FunctionPass {
41 MachineBasicBlock *BB;
43 SelectionDAGISel(TargetLowering &tli) : TLI(tli) {}
45 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
47 virtual bool runOnFunction(Function &Fn);
49 unsigned MakeReg(MVT::ValueType VT);
51 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
52 virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;
54 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
55 /// addressing mode, according to the specified constraint code. If this does
56 /// not match or is not implemented, return true. The resultant operands
57 /// (which will appear in the machine instruction) should be added to the
59 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
61 std::vector<SDOperand> &OutOps,
66 /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
67 /// to use for this target when scheduling the DAG.
68 virtual HazardRecognizer *CreateTargetHazardRecognizer();
70 /// CaseBlock - This structure is used to communicate between SDLowering and
71 /// SDISel for the code generation of additional basic blocks needed by multi-
72 /// case switch statements.
74 CaseBlock(ISD::CondCode cc, Value *s, Constant *c, MachineBasicBlock *lhs,
75 MachineBasicBlock *rhs, MachineBasicBlock *me) :
76 CC(cc), SwitchV(s), CaseC(c), LHSBB(lhs), RHSBB(rhs), ThisBB(me) {}
77 // CC - the condition code to use for the case block's setcc node
79 // SwitchV - the value to be switched on, 'foo' in switch(foo)
81 // CaseC - the constant the setcc node will compare against SwitchV
83 // LHSBB - the block to branch to if the setcc is true
84 MachineBasicBlock *LHSBB;
85 // RHSBB - the block to branch to if the setcc is false
86 MachineBasicBlock *RHSBB;
87 // ThisBB - the blcok into which to emit the code for the setcc and branches
88 MachineBasicBlock *ThisBB;
92 /// Pick a safe ordering and emit instructions for each target node in the
94 void ScheduleAndEmitDAG(SelectionDAG &DAG);
96 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
97 /// by tblgen. Others should not call it.
98 void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
102 SDOperand CopyValueToVirtualRegister(SelectionDAGLowering &SDL,
103 Value *V, unsigned Reg);
104 void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF,
105 FunctionLoweringInfo &FuncInfo);
107 void BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
108 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
109 FunctionLoweringInfo &FuncInfo);
110 void CodeGenAndEmitDAG(SelectionDAG &DAG);
111 void LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
112 std::vector<SDOperand> &UnorderedChains);
114 /// SwitchCases - Vector of CaseBlock structures used to communicate
115 /// SwitchInst code generation information.
116 std::vector<CaseBlock> SwitchCases;
121 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */