1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAGISEL_H
18 #include "llvm/CodeGen/MachineFunctionPass.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/IR/BasicBlock.h"
21 #include "llvm/Pass.h"
25 class SelectionDAGBuilder;
27 class MachineRegisterInfo;
28 class MachineBasicBlock;
29 class MachineFunction;
32 class TargetLibraryInfo;
33 class TargetTransformInfo;
34 class FunctionLoweringInfo;
35 class ScheduleHazardRecognizer;
37 class ScheduleDAGSDNodes;
40 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
41 /// pattern-matching instruction selectors.
42 class SelectionDAGISel : public MachineFunctionPass {
45 const TargetLibraryInfo *LibInfo;
46 const TargetTransformInfo *TTI;
47 FunctionLoweringInfo *FuncInfo;
49 MachineRegisterInfo *RegInfo;
51 SelectionDAGBuilder *SDB;
54 CodeGenOpt::Level OptLevel;
57 explicit SelectionDAGISel(TargetMachine &tm,
58 CodeGenOpt::Level OL = CodeGenOpt::Default);
59 virtual ~SelectionDAGISel();
61 const TargetLowering *getTargetLowering() const {
62 return TM.getTargetLowering();
65 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
67 virtual bool runOnMachineFunction(MachineFunction &MF);
69 virtual void EmitFunctionEntryCode() {}
71 /// PreprocessISelDAG - This hook allows targets to hack on the graph before
72 /// instruction selection starts.
73 virtual void PreprocessISelDAG() {}
75 /// PostprocessISelDAG() - This hook allows the target to hack on the graph
76 /// right after selection.
77 virtual void PostprocessISelDAG() {}
79 /// Select - Main hook targets implement to select a node.
80 virtual SDNode *Select(SDNode *N) = 0;
82 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
83 /// addressing mode, according to the specified constraint code. If this does
84 /// not match or is not implemented, return true. The resultant operands
85 /// (which will appear in the machine instruction) should be added to the
87 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
89 std::vector<SDValue> &OutOps) {
93 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
94 /// operand node N of U during instruction selection that starts at Root.
95 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
97 /// IsLegalToFold - Returns true if the specific operand node N of
98 /// U can be folded during instruction selection that starts at Root.
99 /// FIXME: This is a static member function because the MSP430/X86
100 /// targets, which uses it during isel. This could become a proper member.
101 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
102 CodeGenOpt::Level OptLevel,
103 bool IgnoreChains = false);
105 // Opcodes used by the DAG state machine:
106 enum BuiltinOpcodes {
109 OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3,
110 OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7,
112 OPC_CaptureGlueInput,
116 OPC_CheckPatternPredicate,
122 OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type,
123 OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type,
124 OPC_CheckChild6Type, OPC_CheckChild7Type,
129 OPC_CheckAndImm, OPC_CheckOrImm,
130 OPC_CheckFoldableChainNode,
135 OPC_EmitConvertToTarget,
136 OPC_EmitMergeInputChains,
137 OPC_EmitMergeInputChains1_0,
138 OPC_EmitMergeInputChains1_1,
148 OPFL_None = 0, // Node has no chain or glue input and isn't variadic.
149 OPFL_Chain = 1, // Node has a chain input.
150 OPFL_GlueInput = 2, // Node has a glue input.
151 OPFL_GlueOutput = 4, // Node has a glue output.
152 OPFL_MemRefs = 8, // Node gets accumulated MemRefs.
153 OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs.
154 OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs.
155 OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs.
156 OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs.
157 OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs.
158 OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs.
159 OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs.
161 OPFL_VariadicInfo = OPFL_Variadic6
164 /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
165 /// number of fixed arity values that should be skipped when copying from the
167 static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
168 return ((Flags&OPFL_VariadicInfo) >> 4)-1;
173 /// DAGSize - Size of DAG being instruction selected.
177 /// ReplaceUses - replace all uses of the old node F with the use
178 /// of the new node T.
179 void ReplaceUses(SDValue F, SDValue T) {
180 CurDAG->ReplaceAllUsesOfValueWith(F, T);
183 /// ReplaceUses - replace all uses of the old nodes F with the use
184 /// of the new nodes T.
185 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
186 CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num);
189 /// ReplaceUses - replace all uses of the old node F with the use
190 /// of the new node T.
191 void ReplaceUses(SDNode *F, SDNode *T) {
192 CurDAG->ReplaceAllUsesWith(F, T);
196 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
197 /// by tblgen. Others should not call it.
198 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
202 // Calls to these predicates are generated by tblgen.
203 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
204 int64_t DesiredMaskS) const;
205 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
206 int64_t DesiredMaskS) const;
209 /// CheckPatternPredicate - This function is generated by tblgen in the
210 /// target. It runs the specified pattern predicate and returns true if it
211 /// succeeds or false if it fails. The number is a private implementation
212 /// detail to the code tblgen produces.
213 virtual bool CheckPatternPredicate(unsigned PredNo) const {
214 llvm_unreachable("Tblgen should generate the implementation of this!");
217 /// CheckNodePredicate - This function is generated by tblgen in the target.
218 /// It runs node predicate number PredNo and returns true if it succeeds or
219 /// false if it fails. The number is a private implementation
220 /// detail to the code tblgen produces.
221 virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
222 llvm_unreachable("Tblgen should generate the implementation of this!");
225 virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,
227 SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {
228 llvm_unreachable("Tblgen should generate the implementation of this!");
231 virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
232 llvm_unreachable("Tblgen should generate this!");
235 SDNode *SelectCodeCommon(SDNode *NodeToMatch,
236 const unsigned char *MatcherTable,
241 // Calls to these functions are generated by tblgen.
242 SDNode *Select_INLINEASM(SDNode *N);
243 SDNode *Select_UNDEF(SDNode *N);
244 void CannotYetSelect(SDNode *N);
247 void DoInstructionSelection();
248 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTs,
249 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo);
251 void PrepareEHLandingPad();
253 /// \brief Perform instruction selection on all basic blocks in the function.
254 void SelectAllBasicBlocks(const Function &Fn);
256 /// \brief Perform instruction selection on a single basic block, for
257 /// instructions between \p Begin and \p End. \p HadTailCall will be set
258 /// to true if a call in the block was translated as a tail call.
259 void SelectBasicBlock(BasicBlock::const_iterator Begin,
260 BasicBlock::const_iterator End,
262 void FinishBasicBlock();
264 void CodeGenAndEmitDAG();
266 /// \brief Generate instructions for lowering the incoming arguments of the
268 void LowerArguments(const Function &F);
270 void ComputeLiveOutVRegInfo();
272 /// Create the scheduler. If a specific scheduler was specified
273 /// via the SchedulerRegistry, use it, otherwise select the
274 /// one preferred by the target.
276 ScheduleDAGSDNodes *CreateScheduler();
278 /// OpcodeOffset - This is a cache used to dispatch efficiently into isel
279 /// state machines that start with a OPC_SwitchOpcode node.
280 std::vector<unsigned> OpcodeOffset;
282 void UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
283 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
284 SDValue InputGlue, const SmallVectorImpl<SDNode*> &F,
291 #endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */