1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
18 #include "llvm/Pass.h"
19 #include "llvm/Constant.h"
20 #include "llvm/CodeGen/SelectionDAGNodes.h"
25 class SelectionDAGLowering;
28 class MachineBasicBlock;
29 class MachineFunction;
32 class FunctionLoweringInfo;
33 class HazardRecognizer;
35 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
36 /// pattern-matching instruction selectors.
37 class SelectionDAGISel : public FunctionPass {
42 MachineBasicBlock *BB;
43 bool FoldNodeInFlight;
45 SelectionDAGISel(TargetLowering &tli) : TLI(tli), JT(0,0,0,0) {}
47 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
49 virtual bool runOnFunction(Function &Fn);
51 unsigned MakeReg(MVT::ValueType VT);
53 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
54 virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;
56 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
57 /// addressing mode, according to the specified constraint code. If this does
58 /// not match or is not implemented, return true. The resultant operands
59 /// (which will appear in the machine instruction) should be added to the
61 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
63 std::vector<SDOperand> &OutOps,
68 /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
69 /// to use for this target when scheduling the DAG.
70 virtual HazardRecognizer *CreateTargetHazardRecognizer();
72 /// CaseBlock - This structure is used to communicate between SDLowering and
73 /// SDISel for the code generation of additional basic blocks needed by multi-
74 /// case switch statements.
76 CaseBlock(ISD::CondCode cc, Value *s, Constant *c, MachineBasicBlock *lhs,
77 MachineBasicBlock *rhs, MachineBasicBlock *me) :
78 CC(cc), SwitchV(s), CaseC(c), LHSBB(lhs), RHSBB(rhs), ThisBB(me) {}
79 // CC - the condition code to use for the case block's setcc node
81 // SwitchV - the value to be switched on, 'foo' in switch(foo)
83 // CaseC - the constant the setcc node will compare against SwitchV
85 // LHSBB - the block to branch to if the setcc is true
86 MachineBasicBlock *LHSBB;
87 // RHSBB - the block to branch to if the setcc is false
88 MachineBasicBlock *RHSBB;
89 // ThisBB - the blcok into which to emit the code for the setcc and branches
90 MachineBasicBlock *ThisBB;
93 JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
94 MachineBasicBlock *D) : Reg(R), JTI(J), MBB(M), Default(D) {}
95 // Reg - the virtual register containing the index of the jump table entry
98 // JTI - the JumpTableIndex for this jump table in the function.
100 // MBB - the MBB into which to emit the code for the indirect jump.
101 MachineBasicBlock *MBB;
102 // Default - the MBB of the default bb, which is a successor of the range
103 // check MBB. This is when updating PHI nodes in successors.
104 MachineBasicBlock *Default;
105 // SuccMBBs - a vector of unique successor MBBs used for updating CFG info
107 std::set<MachineBasicBlock*> SuccMBBs;
111 /// Pick a safe ordering and emit instructions for each target node in the
113 void ScheduleAndEmitDAG(SelectionDAG &DAG);
115 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
116 /// by tblgen. Others should not call it.
117 void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
121 SDOperand CopyValueToVirtualRegister(SelectionDAGLowering &SDL,
122 Value *V, unsigned Reg);
123 void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF,
124 FunctionLoweringInfo &FuncInfo);
126 void BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
127 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
128 FunctionLoweringInfo &FuncInfo);
129 void CodeGenAndEmitDAG(SelectionDAG &DAG);
130 void LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
131 std::vector<SDOperand> &UnorderedChains);
133 /// SwitchCases - Vector of CaseBlock structures used to communicate
134 /// SwitchInst code generation information.
135 std::vector<CaseBlock> SwitchCases;
137 /// JT - Record which holds necessary information for emitting a jump table
143 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */