1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
18 #include "llvm/Pass.h"
19 #include "llvm/Constant.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/SelectionDAGNodes.h"
24 class SelectionDAGLowering;
26 class MachineRegisterInfo;
27 class MachineBasicBlock;
28 class MachineFunction;
31 class FunctionLoweringInfo;
32 class HazardRecognizer;
33 class CollectorMetadata;
35 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
36 /// pattern-matching instruction selectors.
37 class SelectionDAGISel : public FunctionPass {
40 MachineRegisterInfo *RegInfo;
42 MachineBasicBlock *BB;
44 std::vector<SDNode*> TopOrder;
46 CollectorMetadata *GCI;
49 explicit SelectionDAGISel(TargetLowering &tli) :
50 FunctionPass((intptr_t)&ID), TLI(tli), DAGSize(0), GCI(0) {}
52 TargetLowering &getTargetLowering() { return TLI; }
54 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
56 virtual bool runOnFunction(Function &Fn);
58 unsigned MakeReg(MVT VT);
60 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
61 virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;
62 virtual void SelectRootInit() {
63 DAGSize = CurDAG->AssignTopologicalOrder(TopOrder);
66 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
67 /// addressing mode, according to the specified constraint code. If this does
68 /// not match or is not implemented, return true. The resultant operands
69 /// (which will appear in the machine instruction) should be added to the
71 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
73 std::vector<SDOperand> &OutOps,
78 /// CanBeFoldedBy - Returns true if the specific operand node N of U can be
79 /// folded during instruction selection that starts at Root?
80 virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const {
84 /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
85 /// to use for this target when scheduling the DAG.
86 virtual HazardRecognizer *CreateTargetHazardRecognizer();
88 /// CaseBlock - This structure is used to communicate between SDLowering and
89 /// SDISel for the code generation of additional basic blocks needed by multi-
90 /// case switch statements.
92 CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle,
93 MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
94 MachineBasicBlock *me)
95 : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
96 TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
97 // CC - the condition code to use for the case block's setcc node
99 // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
100 // Emit by default LHS op RHS. MHS is used for range comparisons:
101 // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
102 Value *CmpLHS, *CmpMHS, *CmpRHS;
103 // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
104 MachineBasicBlock *TrueBB, *FalseBB;
105 // ThisBB - the block into which to emit the code for the setcc and branches
106 MachineBasicBlock *ThisBB;
109 JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
110 MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
112 /// Reg - the virtual register containing the index of the jump table entry
115 /// JTI - the JumpTableIndex for this jump table in the function.
117 /// MBB - the MBB into which to emit the code for the indirect jump.
118 MachineBasicBlock *MBB;
119 /// Default - the MBB of the default bb, which is a successor of the range
120 /// check MBB. This is when updating PHI nodes in successors.
121 MachineBasicBlock *Default;
123 struct JumpTableHeader {
124 JumpTableHeader(uint64_t F, uint64_t L, Value* SV, MachineBasicBlock* H,
126 First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
130 MachineBasicBlock *HeaderBB;
133 typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
136 BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
137 Mask(M), ThisBB(T), TargetBB(Tr) { }
139 MachineBasicBlock* ThisBB;
140 MachineBasicBlock* TargetBB;
143 typedef SmallVector<BitTestCase, 3> BitTestInfo;
145 struct BitTestBlock {
146 BitTestBlock(uint64_t F, uint64_t R, Value* SV,
148 MachineBasicBlock* P, MachineBasicBlock* D,
149 const BitTestInfo& C):
150 First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
151 Parent(P), Default(D), Cases(C) { }
157 MachineBasicBlock *Parent;
158 MachineBasicBlock *Default;
163 /// Pick a safe ordering and emit instructions for each target node in the
165 void ScheduleAndEmitDAG(SelectionDAG &DAG);
167 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
168 /// by tblgen. Others should not call it.
169 void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
172 // Calls to these predicates are generated by tblgen.
173 bool CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
174 int64_t DesiredMaskS) const;
175 bool CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
176 int64_t DesiredMaskS) const;
179 void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF,
180 FunctionLoweringInfo &FuncInfo);
182 void BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
183 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
184 FunctionLoweringInfo &FuncInfo);
185 void CodeGenAndEmitDAG(SelectionDAG &DAG);
186 void LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL);
188 void ComputeLiveOutVRegInfo(SelectionDAG &DAG);
190 /// SwitchCases - Vector of CaseBlock structures used to communicate
191 /// SwitchInst code generation information.
192 std::vector<CaseBlock> SwitchCases;
194 /// JTCases - Vector of JumpTable structures which holds necessary information
195 /// for emitting a jump tables during SwitchInst code generation.
196 std::vector<JumpTableBlock> JTCases;
198 std::vector<BitTestBlock> BitTestCases;
203 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */