1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
18 #include "llvm/Pass.h"
19 #include "llvm/Constant.h"
20 #include "llvm/CodeGen/SelectionDAGNodes.h"
25 class SelectionDAGLowering;
28 class MachineBasicBlock;
29 class MachineFunction;
32 class FunctionLoweringInfo;
33 class HazardRecognizer;
35 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
36 /// pattern-matching instruction selectors.
37 class SelectionDAGISel : public FunctionPass {
42 MachineBasicBlock *BB;
44 SelectionDAGISel(TargetLowering &tli) : TLI(tli), JT(0,0,0,0) {}
46 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
48 virtual bool runOnFunction(Function &Fn);
50 unsigned MakeReg(MVT::ValueType VT);
52 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
53 virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;
55 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
56 /// addressing mode, according to the specified constraint code. If this does
57 /// not match or is not implemented, return true. The resultant operands
58 /// (which will appear in the machine instruction) should be added to the
60 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
62 std::vector<SDOperand> &OutOps,
67 /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
68 /// to use for this target when scheduling the DAG.
69 virtual HazardRecognizer *CreateTargetHazardRecognizer();
71 /// CaseBlock - This structure is used to communicate between SDLowering and
72 /// SDISel for the code generation of additional basic blocks needed by multi-
73 /// case switch statements.
75 CaseBlock(ISD::CondCode cc, Value *s, Constant *c, MachineBasicBlock *lhs,
76 MachineBasicBlock *rhs, MachineBasicBlock *me) :
77 CC(cc), SwitchV(s), CaseC(c), LHSBB(lhs), RHSBB(rhs), ThisBB(me) {}
78 // CC - the condition code to use for the case block's setcc node
80 // SwitchV - the value to be switched on, 'foo' in switch(foo)
82 // CaseC - the constant the setcc node will compare against SwitchV
84 // LHSBB - the block to branch to if the setcc is true
85 MachineBasicBlock *LHSBB;
86 // RHSBB - the block to branch to if the setcc is false
87 MachineBasicBlock *RHSBB;
88 // ThisBB - the blcok into which to emit the code for the setcc and branches
89 MachineBasicBlock *ThisBB;
92 JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
93 MachineBasicBlock *D) : Reg(R), JTI(J), MBB(M), Default(D) {}
94 // Reg - the virtual register containing the index of the jump table entry
97 // JTI - the JumpTableIndex for this jump table in the function.
99 // MBB - the MBB into which to emit the code for the indirect jump.
100 MachineBasicBlock *MBB;
101 // Default - the MBB of the default bb, which is a successor of the range
102 // check MBB. This is when updating PHI nodes in successors.
103 MachineBasicBlock *Default;
104 // SuccMBBs - a vector of unique successor MBBs used for updating CFG info
106 std::set<MachineBasicBlock*> SuccMBBs;
110 /// Pick a safe ordering and emit instructions for each target node in the
112 void ScheduleAndEmitDAG(SelectionDAG &DAG);
114 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
115 /// by tblgen. Others should not call it.
116 void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
120 SDOperand CopyValueToVirtualRegister(SelectionDAGLowering &SDL,
121 Value *V, unsigned Reg);
122 void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF,
123 FunctionLoweringInfo &FuncInfo);
125 void BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
126 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
127 FunctionLoweringInfo &FuncInfo);
128 void CodeGenAndEmitDAG(SelectionDAG &DAG);
129 void LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
130 std::vector<SDOperand> &UnorderedChains);
132 /// SwitchCases - Vector of CaseBlock structures used to communicate
133 /// SwitchInst code generation information.
134 std::vector<CaseBlock> SwitchCases;
136 /// JT - Record which holds necessary information for emitting a jump table
142 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */