1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
18 #include "llvm/Pass.h"
19 #include "llvm/Constant.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/SelectionDAGNodes.h"
24 class SelectionDAGLowering;
27 class MachineBasicBlock;
28 class MachineFunction;
31 class FunctionLoweringInfo;
32 class HazardRecognizer;
34 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
35 /// pattern-matching instruction selectors.
36 class SelectionDAGISel : public FunctionPass {
41 MachineBasicBlock *BB;
42 std::vector<SDNode*> TopOrder;
45 explicit SelectionDAGISel(TargetLowering &tli)
46 : TLI(tli), DAGSize(0), JT(0,0,0,0) {}
48 TargetLowering &getTargetLowering() { return TLI; }
50 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
52 virtual bool runOnFunction(Function &Fn);
54 unsigned MakeReg(MVT::ValueType VT);
56 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
57 virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;
58 virtual void SelectRootInit() {
59 DAGSize = CurDAG->AssignTopologicalOrder(TopOrder);
62 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
63 /// addressing mode, according to the specified constraint code. If this does
64 /// not match or is not implemented, return true. The resultant operands
65 /// (which will appear in the machine instruction) should be added to the
67 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
69 std::vector<SDOperand> &OutOps,
74 /// CanBeFoldedBy - Returns true if the specific operand node N of U can be
75 /// folded during instruction selection that starts at Root?
76 virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) { return true;}
78 /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
79 /// to use for this target when scheduling the DAG.
80 virtual HazardRecognizer *CreateTargetHazardRecognizer();
82 /// CaseBlock - This structure is used to communicate between SDLowering and
83 /// SDISel for the code generation of additional basic blocks needed by multi-
84 /// case switch statements.
86 CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs,
87 MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
88 MachineBasicBlock *me)
89 : CC(cc), CmpLHS(cmplhs), CmpRHS(cmprhs),
90 TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
91 // CC - the condition code to use for the case block's setcc node
93 // CmpLHS/CmpRHS - The LHS/RHS of the comparison to emit.
94 Value *CmpLHS, *CmpRHS;
95 // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
96 MachineBasicBlock *TrueBB, *FalseBB;
97 // ThisBB - the block into which to emit the code for the setcc and branches
98 MachineBasicBlock *ThisBB;
101 JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
102 MachineBasicBlock *D) : Reg(R), JTI(J), MBB(M), Default(D) {}
103 // Reg - the virtual register containing the index of the jump table entry
106 // JTI - the JumpTableIndex for this jump table in the function.
108 // MBB - the MBB into which to emit the code for the indirect jump.
109 MachineBasicBlock *MBB;
110 // Default - the MBB of the default bb, which is a successor of the range
111 // check MBB. This is when updating PHI nodes in successors.
112 MachineBasicBlock *Default;
116 /// Pick a safe ordering and emit instructions for each target node in the
118 void ScheduleAndEmitDAG(SelectionDAG &DAG);
120 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
121 /// by tblgen. Others should not call it.
122 void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
125 // Calls to these predicates are generated by tblgen.
126 bool CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, int64_t DesiredMaskS);
127 bool CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, int64_t DesiredMaskS);
130 void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF,
131 FunctionLoweringInfo &FuncInfo);
133 void BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
134 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
135 FunctionLoweringInfo &FuncInfo);
136 void CodeGenAndEmitDAG(SelectionDAG &DAG);
137 void LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
138 std::vector<SDOperand> &UnorderedChains);
140 /// SwitchCases - Vector of CaseBlock structures used to communicate
141 /// SwitchInst code generation information.
142 std::vector<CaseBlock> SwitchCases;
144 /// JT - Record which holds necessary information for emitting a jump table
150 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */