1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
18 #include "llvm/BasicBlock.h"
19 #include "llvm/Pass.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
25 class SelectionDAGBuilder;
27 class MachineRegisterInfo;
28 class MachineBasicBlock;
29 class MachineFunction;
32 class TargetInstrInfo;
33 class FunctionLoweringInfo;
34 class ScheduleHazardRecognizer;
36 class ScheduleDAGSDNodes;
38 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
39 /// pattern-matching instruction selectors.
40 class SelectionDAGISel : public MachineFunctionPass {
42 const TargetMachine &TM;
43 const TargetLowering &TLI;
44 FunctionLoweringInfo *FuncInfo;
46 MachineRegisterInfo *RegInfo;
48 SelectionDAGBuilder *SDB;
51 CodeGenOpt::Level OptLevel;
54 explicit SelectionDAGISel(TargetMachine &tm,
55 CodeGenOpt::Level OL = CodeGenOpt::Default);
56 virtual ~SelectionDAGISel();
58 const TargetLowering &getTargetLowering() { return TLI; }
60 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
62 virtual bool runOnMachineFunction(MachineFunction &MF);
64 virtual void EmitFunctionEntryCode() {}
66 /// PreprocessISelDAG - This hook allows targets to hack on the graph before
67 /// instruction selection starts.
68 virtual void PreprocessISelDAG() {}
70 /// PostprocessISelDAG() - This hook allows the target to hack on the graph
71 /// right after selection.
72 virtual void PostprocessISelDAG() {}
74 /// Select - Main hook targets implement to select a node.
75 virtual SDNode *Select(SDNode *N) = 0;
77 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
78 /// addressing mode, according to the specified constraint code. If this does
79 /// not match or is not implemented, return true. The resultant operands
80 /// (which will appear in the machine instruction) should be added to the
82 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
84 std::vector<SDValue> &OutOps) {
88 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
89 /// operand node N of U during instruction selection that starts at Root.
90 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
92 /// IsLegalToFold - Returns true if the specific operand node N of
93 /// U can be folded during instruction selection that starts at Root.
94 /// FIXME: This is a static member function because the PIC16 target,
95 /// which uses it during lowering.
96 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
97 CodeGenOpt::Level OptLevel,
98 bool IgnoreChains = false);
100 /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
101 /// to use for this target when scheduling the DAG.
102 virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer();
105 // Opcodes used by the DAG state machine:
106 enum BuiltinOpcodes {
109 OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3,
110 OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7,
112 OPC_CaptureFlagInput,
116 OPC_CheckPatternPredicate,
122 OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type,
123 OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type,
124 OPC_CheckChild6Type, OPC_CheckChild7Type,
129 OPC_CheckAndImm, OPC_CheckOrImm,
130 OPC_CheckFoldableChainNode,
134 OPC_EmitConvertToTarget,
135 OPC_EmitMergeInputChains,
136 OPC_EmitMergeInputChains1_0,
137 OPC_EmitMergeInputChains1_1,
147 OPFL_None = 0, // Node has no chain or flag input and isn't variadic.
148 OPFL_Chain = 1, // Node has a chain input.
149 OPFL_FlagInput = 2, // Node has a flag input.
150 OPFL_FlagOutput = 4, // Node has a flag output.
151 OPFL_MemRefs = 8, // Node gets accumulated MemRefs.
152 OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs.
153 OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs.
154 OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs.
155 OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs.
156 OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs.
157 OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs.
158 OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs.
160 OPFL_VariadicInfo = OPFL_Variadic6
163 /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
164 /// number of fixed arity values that should be skipped when copying from the
166 static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
167 return ((Flags&OPFL_VariadicInfo) >> 4)-1;
172 /// DAGSize - Size of DAG being instruction selected.
176 /// ISelPosition - Node iterator marking the current position of
177 /// instruction selection as it procedes through the topologically-sorted
179 SelectionDAG::allnodes_iterator ISelPosition;
182 /// ISelUpdater - helper class to handle updates of the
183 /// instruction selection graph.
184 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
185 SelectionDAG::allnodes_iterator &ISelPosition;
187 explicit ISelUpdater(SelectionDAG::allnodes_iterator &isp)
188 : ISelPosition(isp) {}
190 /// NodeDeleted - Handle nodes deleted from the graph. If the
191 /// node being deleted is the current ISelPosition node, update
194 virtual void NodeDeleted(SDNode *N, SDNode *E) {
195 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
199 /// NodeUpdated - Ignore updates for now.
200 virtual void NodeUpdated(SDNode *N) {}
203 /// ReplaceUses - replace all uses of the old node F with the use
204 /// of the new node T.
205 void ReplaceUses(SDValue F, SDValue T) {
206 ISelUpdater ISU(ISelPosition);
207 CurDAG->ReplaceAllUsesOfValueWith(F, T, &ISU);
210 /// ReplaceUses - replace all uses of the old nodes F with the use
211 /// of the new nodes T.
212 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
213 ISelUpdater ISU(ISelPosition);
214 CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num, &ISU);
217 /// ReplaceUses - replace all uses of the old node F with the use
218 /// of the new node T.
219 void ReplaceUses(SDNode *F, SDNode *T) {
220 ISelUpdater ISU(ISelPosition);
221 CurDAG->ReplaceAllUsesWith(F, T, &ISU);
225 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
226 /// by tblgen. Others should not call it.
227 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
231 // Calls to these predicates are generated by tblgen.
232 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
233 int64_t DesiredMaskS) const;
234 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
235 int64_t DesiredMaskS) const;
238 /// CheckPatternPredicate - This function is generated by tblgen in the
239 /// target. It runs the specified pattern predicate and returns true if it
240 /// succeeds or false if it fails. The number is a private implementation
241 /// detail to the code tblgen produces.
242 virtual bool CheckPatternPredicate(unsigned PredNo) const {
243 assert(0 && "Tblgen should generate the implementation of this!");
247 /// CheckNodePredicate - This function is generated by tblgen in the target.
248 /// It runs node predicate number PredNo and returns true if it succeeds or
249 /// false if it fails. The number is a private implementation
250 /// detail to the code tblgen produces.
251 virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
252 assert(0 && "Tblgen should generate the implementation of this!");
256 virtual bool CheckComplexPattern(SDNode *Root, SDValue N, unsigned PatternNo,
257 SmallVectorImpl<SDValue> &Result) {
258 assert(0 && "Tblgen should generate the implementation of this!");
262 virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
263 assert(0 && "Tblgen shoudl generate this!");
267 SDNode *SelectCodeCommon(SDNode *NodeToMatch,
268 const unsigned char *MatcherTable,
273 // Calls to these functions are generated by tblgen.
274 SDNode *Select_INLINEASM(SDNode *N);
275 SDNode *Select_UNDEF(SDNode *N);
276 void CannotYetSelect(SDNode *N);
279 void DoInstructionSelection();
280 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTs,
281 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo);
283 void PrepareEHLandingPad(MachineBasicBlock *BB);
284 void SelectAllBasicBlocks(const Function &Fn);
285 void FinishBasicBlock(MachineBasicBlock *BB);
287 void SelectBasicBlock(MachineBasicBlock *BB,
288 const BasicBlock *LLVMBB,
289 BasicBlock::const_iterator Begin,
290 BasicBlock::const_iterator End,
292 void CodeGenAndEmitDAG(MachineBasicBlock *BB);
293 void LowerArguments(const BasicBlock *BB);
295 void ShrinkDemandedOps();
296 void ComputeLiveOutVRegInfo();
298 void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
300 bool HandlePHINodesInSuccessorBlocksFast(const BasicBlock *LLVMBB,
303 /// Create the scheduler. If a specific scheduler was specified
304 /// via the SchedulerRegistry, use it, otherwise select the
305 /// one preferred by the target.
307 ScheduleDAGSDNodes *CreateScheduler();
309 /// OpcodeOffset - This is a cache used to dispatch efficiently into isel
310 /// state machines that start with a OPC_SwitchOpcode node.
311 std::vector<unsigned> OpcodeOffset;
313 void UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
314 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
315 SDValue InputFlag,const SmallVectorImpl<SDNode*> &F,
322 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */