1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
18 #include "llvm/BasicBlock.h"
19 #include "llvm/Pass.h"
20 #include "llvm/Constant.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
26 class SelectionDAGBuilder;
28 class MachineRegisterInfo;
29 class MachineBasicBlock;
30 class MachineFunction;
32 class MachineModuleInfo;
35 class TargetInstrInfo;
36 class FunctionLoweringInfo;
37 class ScheduleHazardRecognizer;
39 class ScheduleDAGSDNodes;
41 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
42 /// pattern-matching instruction selectors.
43 class SelectionDAGISel : public MachineFunctionPass {
45 const TargetMachine &TM;
47 FunctionLoweringInfo *FuncInfo;
49 MachineRegisterInfo *RegInfo;
51 SelectionDAGBuilder *SDB;
52 MachineBasicBlock *BB;
55 CodeGenOpt::Level OptLevel;
58 explicit SelectionDAGISel(TargetMachine &tm,
59 CodeGenOpt::Level OL = CodeGenOpt::Default);
60 virtual ~SelectionDAGISel();
62 TargetLowering &getTargetLowering() { return TLI; }
64 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
66 virtual bool runOnMachineFunction(MachineFunction &MF);
68 unsigned MakeReg(EVT VT);
70 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
71 virtual void InstructionSelect() = 0;
73 void SelectRootInit() {
74 DAGSize = CurDAG->AssignTopologicalOrder();
77 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
78 /// addressing mode, according to the specified constraint code. If this does
79 /// not match or is not implemented, return true. The resultant operands
80 /// (which will appear in the machine instruction) should be added to the
82 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
84 std::vector<SDValue> &OutOps) {
88 /// IsLegalAndProfitableToFold - Returns true if the specific operand node N of
89 /// U can be folded during instruction selection that starts at Root and
90 /// folding N is profitable.
92 bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const;
94 /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
95 /// to use for this target when scheduling the DAG.
96 virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer();
99 /// DAGSize - Size of DAG being instruction selected.
103 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
104 /// by tblgen. Others should not call it.
105 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
107 // Calls to these predicates are generated by tblgen.
108 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
109 int64_t DesiredMaskS) const;
110 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
111 int64_t DesiredMaskS) const;
113 // Calls to these functions are generated by tblgen.
114 SDNode *Select_INLINEASM(SDNode *N);
115 SDNode *Select_UNDEF(SDNode *N);
116 SDNode *Select_EH_LABEL(SDNode *N);
117 void CannotYetSelect(SDNode *N);
118 void CannotYetSelectIntrinsic(SDNode *N);
121 void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
122 MachineModuleInfo *MMI,
124 const TargetInstrInfo &TII);
125 void FinishBasicBlock();
127 void SelectBasicBlock(BasicBlock *LLVMBB,
128 BasicBlock::iterator Begin,
129 BasicBlock::iterator End,
131 void CodeGenAndEmitDAG();
132 void LowerArguments(BasicBlock *BB);
134 void ComputeLiveOutVRegInfo();
136 void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB);
138 bool HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, FastISel *F);
140 /// Create the scheduler. If a specific scheduler was specified
141 /// via the SchedulerRegistry, use it, otherwise select the
142 /// one preferred by the target.
144 ScheduleDAGSDNodes *CreateScheduler();
149 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */