1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
18 #include "llvm/BasicBlock.h"
19 #include "llvm/Pass.h"
20 #include "llvm/Constant.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
25 class SelectionDAGLowering;
27 class MachineRegisterInfo;
28 class MachineBasicBlock;
29 class MachineFunction;
31 class MachineModuleInfo;
34 class TargetInstrInfo;
35 class FunctionLoweringInfo;
36 class ScheduleHazardRecognizer;
38 class ScheduleDAGSDNodes;
40 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
41 /// pattern-matching instruction selectors.
42 class SelectionDAGISel : public FunctionPass {
44 const TargetMachine &TM;
46 FunctionLoweringInfo *FuncInfo;
48 MachineRegisterInfo *RegInfo;
50 SelectionDAGLowering *SDL;
51 MachineBasicBlock *BB;
57 explicit SelectionDAGISel(TargetMachine &tm, bool fast = false);
58 virtual ~SelectionDAGISel();
60 TargetLowering &getTargetLowering() { return TLI; }
62 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
64 virtual bool runOnFunction(Function &Fn);
66 unsigned MakeReg(MVT VT);
68 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
69 virtual void InstructionSelect() = 0;
71 void SelectRootInit() {
72 DAGSize = CurDAG->AssignTopologicalOrder();
75 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
76 /// addressing mode, according to the specified constraint code. If this does
77 /// not match or is not implemented, return true. The resultant operands
78 /// (which will appear in the machine instruction) should be added to the
80 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
82 std::vector<SDValue> &OutOps) {
86 /// IsLegalAndProfitableToFold - Returns true if the specific operand node N of
87 /// U can be folded during instruction selection that starts at Root and
88 /// folding N is profitable.
90 bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const {
94 /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
95 /// to use for this target when scheduling the DAG.
96 virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer();
99 /// DAGSize - Size of DAG being instruction selected.
103 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
104 /// by tblgen. Others should not call it.
105 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
107 // Calls to these predicates are generated by tblgen.
108 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
109 int64_t DesiredMaskS) const;
110 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
111 int64_t DesiredMaskS) const;
114 void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
115 MachineModuleInfo *MMI,
117 const TargetInstrInfo &TII);
118 void FinishBasicBlock();
120 void SelectBasicBlock(BasicBlock *LLVMBB,
121 BasicBlock::iterator Begin,
122 BasicBlock::iterator End);
123 void CodeGenAndEmitDAG();
124 void LowerArguments(BasicBlock *BB);
126 void ComputeLiveOutVRegInfo();
128 void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB);
130 bool HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, FastISel *F);
132 /// Create the scheduler. If a specific scheduler was specified
133 /// via the SchedulerRegistry, use it, otherwise select the
134 /// one preferred by the target.
136 ScheduleDAGSDNodes *CreateScheduler();
141 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */