1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
18 #include "llvm/Pass.h"
19 #include "llvm/Constant.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/SelectionDAGNodes.h"
24 class SelectionDAGLowering;
27 class MachineBasicBlock;
28 class MachineFunction;
31 class FunctionLoweringInfo;
32 class HazardRecognizer;
34 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
35 /// pattern-matching instruction selectors.
36 class SelectionDAGISel : public FunctionPass {
41 MachineBasicBlock *BB;
42 std::vector<SDNode*> TopOrder;
46 explicit SelectionDAGISel(TargetLowering &tli) :
47 FunctionPass((intptr_t)&ID), TLI(tli), DAGSize(0) {}
49 TargetLowering &getTargetLowering() { return TLI; }
51 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
53 virtual bool runOnFunction(Function &Fn);
55 unsigned MakeReg(MVT::ValueType VT);
57 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
58 virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;
59 virtual void SelectRootInit() {
60 DAGSize = CurDAG->AssignTopologicalOrder(TopOrder);
63 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
64 /// addressing mode, according to the specified constraint code. If this does
65 /// not match or is not implemented, return true. The resultant operands
66 /// (which will appear in the machine instruction) should be added to the
68 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
70 std::vector<SDOperand> &OutOps,
75 /// CanBeFoldedBy - Returns true if the specific operand node N of U can be
76 /// folded during instruction selection that starts at Root?
77 virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) { return true;}
79 /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
80 /// to use for this target when scheduling the DAG.
81 virtual HazardRecognizer *CreateTargetHazardRecognizer();
83 /// CaseBlock - This structure is used to communicate between SDLowering and
84 /// SDISel for the code generation of additional basic blocks needed by multi-
85 /// case switch statements.
87 CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle,
88 MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
89 MachineBasicBlock *me)
90 : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
91 TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
92 // CC - the condition code to use for the case block's setcc node
94 // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
95 // Emit by default LHS op RHS. MHS is used for range comparisons:
96 // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
97 Value *CmpLHS, *CmpMHS, *CmpRHS;
98 // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
99 MachineBasicBlock *TrueBB, *FalseBB;
100 // ThisBB - the block into which to emit the code for the setcc and branches
101 MachineBasicBlock *ThisBB;
104 JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
105 MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {};
107 /// Reg - the virtual register containing the index of the jump table entry
110 /// JTI - the JumpTableIndex for this jump table in the function.
112 /// MBB - the MBB into which to emit the code for the indirect jump.
113 MachineBasicBlock *MBB;
114 /// Default - the MBB of the default bb, which is a successor of the range
115 /// check MBB. This is when updating PHI nodes in successors.
116 MachineBasicBlock *Default;
118 struct JumpTableHeader {
119 JumpTableHeader(uint64_t F, uint64_t L, Value* SV, MachineBasicBlock* H,
121 First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {};
125 MachineBasicBlock *HeaderBB;
128 typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
131 BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
132 Mask(M), ThisBB(T), TargetBB(Tr) { };
134 MachineBasicBlock* ThisBB;
135 MachineBasicBlock* TargetBB;
138 typedef SmallVector<BitTestCase, 3> BitTestInfo;
140 struct BitTestBlock {
141 BitTestBlock(uint64_t F, uint64_t R, Value* SV,
143 MachineBasicBlock* P, MachineBasicBlock* D,
144 const BitTestInfo& C):
145 First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
146 Parent(P), Default(D), Cases(C) { };
152 MachineBasicBlock *Parent;
153 MachineBasicBlock *Default;
157 /// Pick a safe ordering and emit instructions for each target node in the
159 void ScheduleAndEmitDAG(SelectionDAG &DAG);
161 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
162 /// by tblgen. Others should not call it.
163 void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
166 // Calls to these predicates are generated by tblgen.
167 bool CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, int64_t DesiredMaskS);
168 bool CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, int64_t DesiredMaskS);
171 void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF,
172 FunctionLoweringInfo &FuncInfo);
174 void BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
175 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
176 FunctionLoweringInfo &FuncInfo);
177 void CodeGenAndEmitDAG(SelectionDAG &DAG);
178 void LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
179 std::vector<SDOperand> &UnorderedChains);
181 /// SwitchCases - Vector of CaseBlock structures used to communicate
182 /// SwitchInst code generation information.
183 std::vector<CaseBlock> SwitchCases;
185 /// JTCases - Vector of JumpTable structures which holds necessary information
186 /// for emitting a jump tables during SwitchInst code generation.
187 std::vector<JumpTableBlock> JTCases;
189 std::vector<BitTestBlock> BitTestCases;
194 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */