1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAGISEL_H
18 #include "llvm/CodeGen/MachineFunctionPass.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/IR/BasicBlock.h"
21 #include "llvm/Pass.h"
25 class SelectionDAGBuilder;
27 class MachineRegisterInfo;
28 class MachineBasicBlock;
29 class MachineFunction;
32 class TargetLibraryInfo;
33 class FunctionLoweringInfo;
34 class ScheduleHazardRecognizer;
36 class ScheduleDAGSDNodes;
39 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
40 /// pattern-matching instruction selectors.
41 class SelectionDAGISel : public MachineFunctionPass {
44 const TargetLibraryInfo *LibInfo;
45 FunctionLoweringInfo *FuncInfo;
47 MachineRegisterInfo *RegInfo;
49 SelectionDAGBuilder *SDB;
52 CodeGenOpt::Level OptLevel;
55 explicit SelectionDAGISel(TargetMachine &tm,
56 CodeGenOpt::Level OL = CodeGenOpt::Default);
57 virtual ~SelectionDAGISel();
59 const TargetLowering *getTargetLowering() const {
60 return TM.getTargetLowering();
63 void getAnalysisUsage(AnalysisUsage &AU) const override;
65 bool runOnMachineFunction(MachineFunction &MF) override;
67 virtual void EmitFunctionEntryCode() {}
69 /// PreprocessISelDAG - This hook allows targets to hack on the graph before
70 /// instruction selection starts.
71 virtual void PreprocessISelDAG() {}
73 /// PostprocessISelDAG() - This hook allows the target to hack on the graph
74 /// right after selection.
75 virtual void PostprocessISelDAG() {}
77 /// Select - Main hook targets implement to select a node.
78 virtual SDNode *Select(SDNode *N) = 0;
80 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
81 /// addressing mode, according to the specified constraint code. If this does
82 /// not match or is not implemented, return true. The resultant operands
83 /// (which will appear in the machine instruction) should be added to the
85 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
87 std::vector<SDValue> &OutOps) {
91 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
92 /// operand node N of U during instruction selection that starts at Root.
93 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
95 /// IsLegalToFold - Returns true if the specific operand node N of
96 /// U can be folded during instruction selection that starts at Root.
97 /// FIXME: This is a static member function because the MSP430/X86
98 /// targets, which uses it during isel. This could become a proper member.
99 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
100 CodeGenOpt::Level OptLevel,
101 bool IgnoreChains = false);
103 // Opcodes used by the DAG state machine:
104 enum BuiltinOpcodes {
107 OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3,
108 OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7,
110 OPC_CaptureGlueInput,
114 OPC_CheckChild0Same, OPC_CheckChild1Same,
115 OPC_CheckChild2Same, OPC_CheckChild3Same,
116 OPC_CheckPatternPredicate,
122 OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type,
123 OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type,
124 OPC_CheckChild6Type, OPC_CheckChild7Type,
126 OPC_CheckChild0Integer, OPC_CheckChild1Integer, OPC_CheckChild2Integer,
127 OPC_CheckChild3Integer, OPC_CheckChild4Integer,
131 OPC_CheckAndImm, OPC_CheckOrImm,
132 OPC_CheckFoldableChainNode,
137 OPC_EmitConvertToTarget,
138 OPC_EmitMergeInputChains,
139 OPC_EmitMergeInputChains1_0,
140 OPC_EmitMergeInputChains1_1,
150 OPFL_None = 0, // Node has no chain or glue input and isn't variadic.
151 OPFL_Chain = 1, // Node has a chain input.
152 OPFL_GlueInput = 2, // Node has a glue input.
153 OPFL_GlueOutput = 4, // Node has a glue output.
154 OPFL_MemRefs = 8, // Node gets accumulated MemRefs.
155 OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs.
156 OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs.
157 OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs.
158 OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs.
159 OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs.
160 OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs.
161 OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs.
163 OPFL_VariadicInfo = OPFL_Variadic6
166 /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
167 /// number of fixed arity values that should be skipped when copying from the
169 static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
170 return ((Flags&OPFL_VariadicInfo) >> 4)-1;
175 /// DAGSize - Size of DAG being instruction selected.
179 /// ReplaceUses - replace all uses of the old node F with the use
180 /// of the new node T.
181 void ReplaceUses(SDValue F, SDValue T) {
182 CurDAG->ReplaceAllUsesOfValueWith(F, T);
185 /// ReplaceUses - replace all uses of the old nodes F with the use
186 /// of the new nodes T.
187 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
188 CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num);
191 /// ReplaceUses - replace all uses of the old node F with the use
192 /// of the new node T.
193 void ReplaceUses(SDNode *F, SDNode *T) {
194 CurDAG->ReplaceAllUsesWith(F, T);
198 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
199 /// by tblgen. Others should not call it.
200 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
204 // Calls to these predicates are generated by tblgen.
205 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
206 int64_t DesiredMaskS) const;
207 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
208 int64_t DesiredMaskS) const;
211 /// CheckPatternPredicate - This function is generated by tblgen in the
212 /// target. It runs the specified pattern predicate and returns true if it
213 /// succeeds or false if it fails. The number is a private implementation
214 /// detail to the code tblgen produces.
215 virtual bool CheckPatternPredicate(unsigned PredNo) const {
216 llvm_unreachable("Tblgen should generate the implementation of this!");
219 /// CheckNodePredicate - This function is generated by tblgen in the target.
220 /// It runs node predicate number PredNo and returns true if it succeeds or
221 /// false if it fails. The number is a private implementation
222 /// detail to the code tblgen produces.
223 virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
224 llvm_unreachable("Tblgen should generate the implementation of this!");
227 virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,
229 SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {
230 llvm_unreachable("Tblgen should generate the implementation of this!");
233 virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
234 llvm_unreachable("Tblgen should generate this!");
237 SDNode *SelectCodeCommon(SDNode *NodeToMatch,
238 const unsigned char *MatcherTable,
243 // Calls to these functions are generated by tblgen.
244 SDNode *Select_INLINEASM(SDNode *N);
245 SDNode *Select_READ_REGISTER(SDNode *N);
246 SDNode *Select_WRITE_REGISTER(SDNode *N);
247 SDNode *Select_UNDEF(SDNode *N);
248 void CannotYetSelect(SDNode *N);
251 void DoInstructionSelection();
252 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTs,
253 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo);
255 void PrepareEHLandingPad();
257 /// \brief Perform instruction selection on all basic blocks in the function.
258 void SelectAllBasicBlocks(const Function &Fn);
260 /// \brief Perform instruction selection on a single basic block, for
261 /// instructions between \p Begin and \p End. \p HadTailCall will be set
262 /// to true if a call in the block was translated as a tail call.
263 void SelectBasicBlock(BasicBlock::const_iterator Begin,
264 BasicBlock::const_iterator End,
266 void FinishBasicBlock();
268 void CodeGenAndEmitDAG();
270 /// \brief Generate instructions for lowering the incoming arguments of the
272 void LowerArguments(const Function &F);
274 void ComputeLiveOutVRegInfo();
276 /// Create the scheduler. If a specific scheduler was specified
277 /// via the SchedulerRegistry, use it, otherwise select the
278 /// one preferred by the target.
280 ScheduleDAGSDNodes *CreateScheduler();
282 /// OpcodeOffset - This is a cache used to dispatch efficiently into isel
283 /// state machines that start with a OPC_SwitchOpcode node.
284 std::vector<unsigned> OpcodeOffset;
286 void UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
287 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
288 SDValue InputGlue, const SmallVectorImpl<SDNode*> &F,
295 #endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */