1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
18 #include "llvm/Pass.h"
19 #include "llvm/CodeGen/ValueTypes.h"
23 class SelectionDAGLowering;
26 class MachineBasicBlock;
27 class MachineFunction;
30 class FunctionLoweringInfo;
31 class HazardRecognizer;
33 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
34 /// pattern-matching instruction selectors.
35 class SelectionDAGISel : public FunctionPass {
40 MachineBasicBlock *BB;
42 SelectionDAGISel(TargetLowering &tli) : TLI(tli) {}
44 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
46 virtual bool runOnFunction(Function &Fn);
48 unsigned MakeReg(MVT::ValueType VT);
50 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
51 virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;
53 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
54 /// addressing mode, according to the specified constraint code. If this does
55 /// not match or is not implemented, return true. The resultant operands
56 /// (which will appear in the machine instruction) should be added to the
58 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
60 std::vector<SDOperand> &OutOps,
65 /// GetTargetHazardRecognizer - Return the hazard recognizer to use for this
66 /// target when scheduling the DAG.
67 virtual HazardRecognizer &GetTargetHazardRecognizer();
70 /// Pick a safe ordering and emit instructions for each target node in the
72 void ScheduleAndEmitDAG(SelectionDAG &DAG);
74 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
75 /// by tblgen. Others should not call it.
76 void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
80 SDOperand CopyValueToVirtualRegister(SelectionDAGLowering &SDL,
81 Value *V, unsigned Reg);
82 void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF,
83 FunctionLoweringInfo &FuncInfo);
85 void BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
86 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
87 FunctionLoweringInfo &FuncInfo);
88 void LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
89 std::vector<SDOperand> &UnorderedChains);
94 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */