1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
18 #include "llvm/BasicBlock.h"
19 #include "llvm/Pass.h"
20 #include "llvm/Constant.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
26 class SelectionDAGBuilder;
28 class MachineRegisterInfo;
29 class MachineBasicBlock;
30 class MachineFunction;
32 class MachineModuleInfo;
35 class TargetInstrInfo;
36 class FunctionLoweringInfo;
37 class ScheduleHazardRecognizer;
39 class ScheduleDAGSDNodes;
41 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
42 /// pattern-matching instruction selectors.
43 class SelectionDAGISel : public MachineFunctionPass {
45 const TargetMachine &TM;
47 FunctionLoweringInfo *FuncInfo;
49 MachineRegisterInfo *RegInfo;
51 SelectionDAGBuilder *SDB;
52 MachineBasicBlock *BB;
55 CodeGenOpt::Level OptLevel;
58 explicit SelectionDAGISel(TargetMachine &tm,
59 CodeGenOpt::Level OL = CodeGenOpt::Default);
60 virtual ~SelectionDAGISel();
62 TargetLowering &getTargetLowering() { return TLI; }
64 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
66 virtual bool runOnMachineFunction(MachineFunction &MF);
68 unsigned MakeReg(EVT VT);
70 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
72 /// PreprocessISelDAG - This hook allows targets to hack on the graph before
73 /// instruction selection starts.
74 virtual void PreprocessISelDAG() {}
76 /// PostprocessISelDAG() - This hook allows the target to hack on the graph
77 /// right after selection.
78 virtual void PostprocessISelDAG() {}
80 /// Select - Main hook targets implement to select a node.
81 virtual SDNode *Select(SDNode *N) = 0;
83 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
84 /// addressing mode, according to the specified constraint code. If this does
85 /// not match or is not implemented, return true. The resultant operands
86 /// (which will appear in the machine instruction) should be added to the
88 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
90 std::vector<SDValue> &OutOps) {
94 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
95 /// operand node N of U during instruction selection that starts at Root.
96 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
98 /// IsLegalToFold - Returns true if the specific operand node N of
99 /// U can be folded during instruction selection that starts at Root.
100 virtual bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root) const;
102 /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
103 /// to use for this target when scheduling the DAG.
104 virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer();
107 // Opcodes used by the DAG state machine:
108 enum BuiltinOpcodes {
111 OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3,
112 OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7,
114 OPC_CaptureFlagInput,
118 OPC_CheckPatternPredicate,
123 OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type,
124 OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type,
125 OPC_CheckChild6Type, OPC_CheckChild7Type,
130 OPC_CheckAndImm, OPC_CheckOrImm,
131 OPC_CheckFoldableChainNode,
135 OPC_EmitConvertToTarget,
136 OPC_EmitMergeInputChains,
146 OPFL_None = 0, // Node has no chain or flag input and isn't variadic.
147 OPFL_Chain = 1, // Node has a chain input.
148 OPFL_FlagInput = 2, // Node has a flag input.
149 OPFL_FlagOutput = 4, // Node has a flag output.
150 OPFL_MemRefs = 8, // Node gets accumulated MemRefs.
151 OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs.
152 OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs.
153 OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs.
154 OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs.
155 OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs.
156 OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs.
157 OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs.
159 OPFL_VariadicInfo = OPFL_Variadic6
162 /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
163 /// number of fixed arity values that should be skipped when copying from the
165 static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
166 return ((Flags&OPFL_VariadicInfo) >> 4)-1;
171 /// DAGSize - Size of DAG being instruction selected.
175 /// ISelPosition - Node iterator marking the current position of
176 /// instruction selection as it procedes through the topologically-sorted
178 SelectionDAG::allnodes_iterator ISelPosition;
181 /// ISelUpdater - helper class to handle updates of the
182 /// instruction selection graph.
183 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
184 SelectionDAG::allnodes_iterator &ISelPosition;
186 explicit ISelUpdater(SelectionDAG::allnodes_iterator &isp)
187 : ISelPosition(isp) {}
189 /// NodeDeleted - Handle nodes deleted from the graph. If the
190 /// node being deleted is the current ISelPosition node, update
193 virtual void NodeDeleted(SDNode *N, SDNode *E) {
194 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
198 /// NodeUpdated - Ignore updates for now.
199 virtual void NodeUpdated(SDNode *N) {}
202 /// ReplaceUses - replace all uses of the old node F with the use
203 /// of the new node T.
204 void ReplaceUses(SDValue F, SDValue T) {
205 ISelUpdater ISU(ISelPosition);
206 CurDAG->ReplaceAllUsesOfValueWith(F, T, &ISU);
209 /// ReplaceUses - replace all uses of the old nodes F with the use
210 /// of the new nodes T.
211 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
212 ISelUpdater ISU(ISelPosition);
213 CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num, &ISU);
216 /// ReplaceUses - replace all uses of the old node F with the use
217 /// of the new node T.
218 void ReplaceUses(SDNode *F, SDNode *T) {
219 ISelUpdater ISU(ISelPosition);
220 CurDAG->ReplaceAllUsesWith(F, T, &ISU);
224 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
225 /// by tblgen. Others should not call it.
226 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
228 // Calls to these predicates are generated by tblgen.
229 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
230 int64_t DesiredMaskS) const;
231 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
232 int64_t DesiredMaskS) const;
235 /// CheckPatternPredicate - This function is generated by tblgen in the
236 /// target. It runs the specified pattern predicate and returns true if it
237 /// succeeds or false if it fails. The number is a private implementation
238 /// detail to the code tblgen produces.
239 virtual bool CheckPatternPredicate(unsigned PredNo) const {
240 assert(0 && "Tblgen should generate the implementation of this!");
244 /// CheckNodePredicate - This function is generated by tblgen in the target.
245 /// It runs node predicate number PredNo and returns true if it succeeds or
246 /// false if it fails. The number is a private implementation
247 /// detail to the code tblgen produces.
248 virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
249 assert(0 && "Tblgen should generate the implementation of this!");
253 virtual bool CheckComplexPattern(SDNode *Root, SDValue N, unsigned PatternNo,
254 SmallVectorImpl<SDValue> &Result) {
255 assert(0 && "Tblgen should generate the implementation of this!");
259 virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
260 assert(0 && "Tblgen shoudl generate this!");
265 // Calls to these functions are generated by tblgen.
266 SDNode *Select_INLINEASM(SDNode *N);
267 SDNode *Select_UNDEF(SDNode *N);
268 SDNode *Select_EH_LABEL(SDNode *N);
270 SDNode *SelectCodeCommon(SDNode *NodeToMatch,
271 const unsigned char *MatcherTable,
273 void CannotYetSelect(SDNode *N);
274 void CannotYetSelectIntrinsic(SDNode *N);
277 void DoInstructionSelection();
278 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTs,
279 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo);
281 void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
282 MachineModuleInfo *MMI,
284 const TargetInstrInfo &TII);
285 void FinishBasicBlock();
287 void SelectBasicBlock(BasicBlock *LLVMBB,
288 BasicBlock::iterator Begin,
289 BasicBlock::iterator End,
291 void CodeGenAndEmitDAG();
292 void LowerArguments(BasicBlock *BB);
294 void ShrinkDemandedOps();
295 void ComputeLiveOutVRegInfo();
297 void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB);
299 bool HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, FastISel *F);
301 /// Create the scheduler. If a specific scheduler was specified
302 /// via the SchedulerRegistry, use it, otherwise select the
303 /// one preferred by the target.
305 ScheduleDAGSDNodes *CreateScheduler();
307 /// OpcodeOffset - This is a cache used to dispatch efficiently into isel
308 /// state machines that start with a OPC_SwitchOpcode node.
309 std::vector<unsigned> OpcodeOffset;
314 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */