1 //===-- SimpleRegisterCoalescing.h - Register Coalescing --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register copy coalescing phase.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
15 #define LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/LiveInterval.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/RegisterCoalescer.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/IndexedMap.h"
28 class TargetInstrInfo;
31 class SimpleRegisterCoalescing : public MachineFunctionPass,
32 public RegisterCoalescer {
34 const TargetMachine* tm_;
35 const MRegisterInfo* mri_;
36 const TargetInstrInfo* tii_;
40 typedef IndexedMap<unsigned> Reg2RegMap;
43 BitVector allocatableRegs_;
44 DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs_;
46 /// JoinedLIs - Keep track which register intervals have been coalesced
47 /// with other intervals.
51 static char ID; // Pass identifcation, replacement for typeid
52 SimpleRegisterCoalescing() : MachineFunctionPass((intptr_t)&ID) {}
56 unsigned SrcReg, DstReg;
58 CopyRec getCopyRec(MachineInstr *MI, unsigned SrcReg, unsigned DstReg) {
75 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
76 virtual void releaseMemory();
78 /// runOnMachineFunction - pass entry point
79 virtual bool runOnMachineFunction(MachineFunction&);
81 bool coalesceFunction(MachineFunction &mf, RegallocQuery &) {
82 // This runs as an independent pass, so don't do anything.
86 /// print - Implement the dump method.
87 virtual void print(std::ostream &O, const Module* = 0) const;
88 void print(std::ostream *O, const Module* M = 0) const {
93 /// joinIntervals - join compatible live intervals
96 /// CopyCoalesceInMBB - Coalesce copies in the specified MBB, putting
97 /// copies that cannot yet be coalesced into the "TryAgain" list.
98 void CopyCoalesceInMBB(MachineBasicBlock *MBB,
99 std::vector<CopyRec> *TryAgain, bool PhysOnly = false);
101 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
102 /// which are the src/dst of the copy instruction CopyMI. This returns true
103 /// if the copy was successfully coalesced away, or if it is never possible
104 /// to coalesce these this copy, due to register constraints. It returns
105 /// false if it is not currently possible to coalesce this interval, but
106 /// it may be possible if other things get coalesced.
107 bool JoinCopy(MachineInstr *CopyMI, unsigned SrcReg, unsigned DstReg,
108 bool PhysOnly = false);
110 /// JoinIntervals - Attempt to join these two intervals. On failure, this
111 /// returns false. Otherwise, if one of the intervals being joined is a
112 /// physreg, this method always canonicalizes DestInt to be it. The output
113 /// "SrcInt" will not have been modified, so we can use this information
114 /// below to update aliases.
115 bool JoinIntervals(LiveInterval &LHS, LiveInterval &RHS, bool &Swapped);
117 /// SimpleJoin - Attempt to join the specified interval into this one. The
118 /// caller of this method must guarantee that the RHS only contains a single
119 /// value number and that the RHS is not defined by a copy from this
120 /// interval. This returns false if the intervals are not joinable, or it
121 /// joins them and returns true.
122 bool SimpleJoin(LiveInterval &LHS, LiveInterval &RHS);
124 /// Return true if the two specified registers belong to different
125 /// register classes. The registers may be either phys or virt regs.
126 bool differingRegisterClasses(unsigned RegA, unsigned RegB) const;
129 bool AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
130 MachineInstr *CopyMI);
132 /// lastRegisterUse - Returns the last use of the specific register between
133 /// cycles Start and End. It also returns the use operand by reference. It
134 /// returns NULL if there are no uses.
135 MachineInstr *lastRegisterUse(unsigned Start, unsigned End, unsigned Reg,
136 MachineOperand *&MOU);
138 /// findDefOperand - Returns the MachineOperand that is a def of the specific
139 /// register. It returns NULL if the def is not found.
140 MachineOperand *findDefOperand(MachineInstr *MI, unsigned Reg);
142 /// unsetRegisterKill - Unset IsKill property of all uses of the specific
143 /// register of the specific instruction.
144 void unsetRegisterKill(MachineInstr *MI, unsigned Reg);
146 /// unsetRegisterKills - Unset IsKill property of all uses of specific register
147 /// between cycles Start and End.
148 void unsetRegisterKills(unsigned Start, unsigned End, unsigned Reg);
150 /// hasRegisterDef - True if the instruction defines the specific register.
152 bool hasRegisterDef(MachineInstr *MI, unsigned Reg);
154 /// rep - returns the representative of this register
155 unsigned rep(unsigned Reg) {
156 unsigned Rep = r2rMap_[Reg];
158 return r2rMap_[Reg] = rep(Rep);
162 void printRegName(unsigned reg) const;
165 } // End llvm namespace