1 //===-- llvm/CodeGen/TargetSchedule.h - Sched Machine Model -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a wrapper around MCSchedModel that allows the interface to
11 // benefit from information currently only available in TargetInstrInfo.
12 // Ideally, the scheduling interface would be fully defined in the MC layer.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_TARGETSCHEDULE_H
17 #define LLVM_CODEGEN_TARGETSCHEDULE_H
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/MC/MCInstrItineraries.h"
21 #include "llvm/MC/MCSchedule.h"
22 #include "llvm/Target/TargetSubtargetInfo.h"
26 class TargetRegisterInfo;
27 class TargetSubtargetInfo;
28 class TargetInstrInfo;
31 /// Provide an instruction scheduling machine model to CodeGen passes.
32 class TargetSchedModel {
33 // For efficiency, hold a copy of the statically defined MCSchedModel for this
35 MCSchedModel SchedModel;
36 InstrItineraryData InstrItins;
37 const TargetSubtargetInfo *STI;
38 const TargetInstrInfo *TII;
40 SmallVector<unsigned, 16> ResourceFactors;
41 unsigned MicroOpFactor; // Multiply to normalize microops to resource units.
42 unsigned ResourceLCM; // Resource units per cycle. Latency normalization factor.
44 unsigned computeInstrLatency(const MCSchedClassDesc &SCDesc) const;
47 TargetSchedModel(): SchedModel(MCSchedModel::GetDefaultSchedModel()), STI(nullptr), TII(nullptr) {}
49 /// \brief Initialize the machine model for instruction scheduling.
51 /// The machine model API keeps a copy of the top-level MCSchedModel table
52 /// indices and may query TargetSubtargetInfo and TargetInstrInfo to resolve
53 /// dynamic properties.
54 void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti,
55 const TargetInstrInfo *tii);
57 /// Return the MCSchedClassDesc for this instruction.
58 const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const;
60 /// \brief TargetInstrInfo getter.
61 const TargetInstrInfo *getInstrInfo() const { return TII; }
63 /// \brief Return true if this machine model includes an instruction-level
66 /// This is more detailed than the course grain IssueWidth and default
67 /// latency properties, but separate from the per-cycle itinerary data.
68 bool hasInstrSchedModel() const;
70 const MCSchedModel *getMCSchedModel() const { return &SchedModel; }
72 /// \brief Return true if this machine model includes cycle-to-cycle itinerary
75 /// This models scheduling at each stage in the processor pipeline.
76 bool hasInstrItineraries() const;
78 const InstrItineraryData *getInstrItineraries() const {
79 if (hasInstrItineraries())
84 /// \brief Return true if this machine model includes an instruction-level
85 /// scheduling model or cycle-to-cycle itinerary data.
86 bool hasInstrSchedModelOrItineraries() const {
87 return hasInstrSchedModel() || hasInstrItineraries();
90 /// \brief Identify the processor corresponding to the current subtarget.
91 unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
93 /// \brief Maximum number of micro-ops that may be scheduled per cycle.
94 unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
96 /// \brief Return the number of issue slots required for this MI.
97 unsigned getNumMicroOps(const MachineInstr *MI,
98 const MCSchedClassDesc *SC = nullptr) const;
100 /// \brief Get the number of kinds of resources for this target.
101 unsigned getNumProcResourceKinds() const {
102 return SchedModel.getNumProcResourceKinds();
105 /// \brief Get a processor resource by ID for convenience.
106 const MCProcResourceDesc *getProcResource(unsigned PIdx) const {
107 return SchedModel.getProcResource(PIdx);
111 const char *getResourceName(unsigned PIdx) const {
114 return SchedModel.getProcResource(PIdx)->Name;
118 typedef const MCWriteProcResEntry *ProcResIter;
120 // \brief Get an iterator into the processor resources consumed by this
122 ProcResIter getWriteProcResBegin(const MCSchedClassDesc *SC) const {
123 // The subtarget holds a single resource table for all processors.
124 return STI->getWriteProcResBegin(SC);
126 ProcResIter getWriteProcResEnd(const MCSchedClassDesc *SC) const {
127 return STI->getWriteProcResEnd(SC);
130 /// \brief Multiply the number of units consumed for a resource by this factor
131 /// to normalize it relative to other resources.
132 unsigned getResourceFactor(unsigned ResIdx) const {
133 return ResourceFactors[ResIdx];
136 /// \brief Multiply number of micro-ops by this factor to normalize it
137 /// relative to other resources.
138 unsigned getMicroOpFactor() const {
139 return MicroOpFactor;
142 /// \brief Multiply cycle count by this factor to normalize it relative to
143 /// other resources. This is the number of resource units per cycle.
144 unsigned getLatencyFactor() const {
148 /// \brief Number of micro-ops that may be buffered for OOO execution.
149 unsigned getMicroOpBufferSize() const { return SchedModel.MicroOpBufferSize; }
151 /// \brief Number of resource units that may be buffered for OOO execution.
152 /// \return The buffer size in resource units or -1 for unlimited.
153 int getResourceBufferSize(unsigned PIdx) const {
154 return SchedModel.getProcResource(PIdx)->BufferSize;
157 /// \brief Compute operand latency based on the available machine model.
159 /// Compute and return the latency of the given data dependent def and use
160 /// when the operand indices are already known. UseMI may be NULL for an
162 unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
163 const MachineInstr *UseMI, unsigned UseOperIdx)
166 /// \brief Compute the instruction latency based on the available machine
169 /// Compute and return the expected latency of this instruction independent of
170 /// a particular use. computeOperandLatency is the preferred API, but this is
171 /// occasionally useful to help estimate instruction cost.
173 /// If UseDefaultDefLatency is false and no new machine sched model is
174 /// present this method falls back to TII->getInstrLatency with an empty
175 /// instruction itinerary (this is so we preserve the previous behavior of the
176 /// if converter after moving it to TargetSchedModel).
177 unsigned computeInstrLatency(const MachineInstr *MI,
178 bool UseDefaultDefLatency = true) const;
179 unsigned computeInstrLatency(unsigned Opcode) const;
181 /// \brief Output dependency latency of a pair of defs of the same register.
183 /// This is typically one cycle.
184 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
185 const MachineInstr *DepMI) const;